Chip Gallery

Process: 65nm TSMC CMOS process.
Design: Resonant HBC: Hub and Node Transceivers for Power and Data Transfer through the body.
Publications: CICC2021

Process: 65nm TSMC CMOS process.
Design: Bi-Phasic QBC: Implemented Transceiver for EQS Brain-Channel Communication with minimum end-to-end channel loss.
Publications: VLSI2021

Process: 65nm TSMC CMOS process.
Design: Syn-Steller: Synthesizable Digital Signature Attenuation Circuit(DSAC) with Time Varying Transfer Function(TVTF)
Publications: ISSCC2021

Process: 65nm TSMC CMOS process.
Design: CS-Audio: A Compressive Sensing IC with DWT Sparsifier for Audio Compression.
Publications: CICC2021

Process: 65nm TSMC CMOS process.
Design: A Context-Aware Reconfigurable Transmitter
Publications: RFIC2020, JSSC2021

Process: 65nm TSMC CMOS process.
Design: Electro-Quasistatic HBC Node
Publications: JSSC2021

Process: 65nm TSMC CMOS process.
Design: A 41.5pJ/bit, 2.4GHz Digital Friendly Orthgonally Tunable Transceiver SoC.
Publications: CICC2020

Process: 350nm TSMC CMOS, 180nm TSMC CMOS processes.
Design: First monolithically integrated Radiation Sensor + Readout, containing a Floating Gate Radiation Sensor and a sub-1uW
Publications: CICC2019 (Best Paper), JSSC2019

Process: 65nm TSMC CMOS process.
Design: Low-Overhead generic countermeasure for Power and EM side-channel attacks, consisting current domain signature attenuation and low-level routing.
Publications: ISSCC2020.

To be updated

Process: 65nm TSMC CMOS process
Design: Broadband Human Body Communication Transceiver
Publication: CICC 2018 World's lowest-energy Body Area Network (BAN) IC

Process: 14 nm Intel CMOS process
Design: 32 Gbps 4-Channel Capacitive Proximity Communication Transceiver
Publication: ISSCC 2016, JSSC 2016 World's fastest and most-energy efficient mm-scale capacitive Proximity Communication Link

Process: 22 nm Intel CMOS process
Design: 25.6Gb/s Differential and DDR4/GDDR5 Dual-Mode Transmitter
Publication: ISSCC 2014

To be updated

Process: 65 nm TSMC CMOS process
Design: DVH-Receiver with Wideband Jammer Detector
Publication: Shreyas Sen, Ph.D. Thesis, Georgia Tech, 2011 Wideband Jammer detector allowing programmable jammer detection time (5us to 6ms). This allows adaptive receiver power vs. performance trade-off when a jammer is not present

Process: 180 nm National Semiconductor process
Design: Orthogonally Tunable LNA for Zero-margin Receiver
Publication: ISCAS 2011, TCASI 2011 (special issue) Orthogonally tunable LNA that allows independent control of Gain+NF or Linearity with power consumption. This enables dynamically extra power savings in RF receiver in both cases when SNR is high or interference is not present (VIZOR).