New undergraduate-Level Course ECE 337

Engineering Faculty Document No. 2-05

January 17, 2006

Page 1 of 4

TO: The Faculty of the College of Engineering

FROM: The Faculty of the School of Electrical and Computer Engineering

RE: New Undergraduate-Level Course

The faculty of the School of Electrical and Computer Engineering has approved the following new course. This action is now submitted to the Engineering Faculty with a recommendation for approval.

ECE 337 ASIC Design Laboratory

Class 1, Lab 3, Credit 2

Prerequisites: ECE 264 and ECE 270

Course Description: Introduction to standard cell design of VLSI (Very Large Scale Integration) digital circuits using the VHDL hardware description language (Very High Speed Integrated Circuits Hardware Description Language). Emphasis on how to write VHDL that will map readily to hardware. Laboratory experiments using commercial grade computer-aided design (CAD) tools for VHDL based design, schematic based logic entry, logic and VHDL simulation, automatic placement and routing, timing analysis, and testing.

Reason: This is a required course for the Computer Engineering degree, and it will continue to be offered for the foreseeable future.

Course History:  This course was offered as an experimental course as ECE 495D in the Spring 2002, Fall 2002, Spring 2003, Fall 2003, Spring 2004, and Fall 2005 semesters with enrollments of 79, 50, 99, 57, 85, and 32 students respectively.

Mark J.T. Smith

Professor and Head

Engineering Faculty Document No. 2-05

January 17, 2006

Page 2 of 4

Supporting Documentation:

Required Text(s):

1. VHDL for Logic Synthesis, 2nd Edition, Andrew Rushton, John Wiley & Sons, Inc., 1998, ISBN No. 0-471-98325-X.

Recommended Reference(s):

1.      Digital Design Principles and Practices, 4^th Edition, John F. Wakerly, Prentice Hall, 2006, ISBN No. 0-13-186389-4.

Course Outcomes:

A student who successfully fulfills the course requirements will have demonstrated an ability to:

1. understand and use major syntactic elements of VDHL - entities, architectures, processes, functions, common concurrent statements, and common sequential statements.
2. design combinational logic in a variety of styles including: schematic, structural VHDL, and behavioral VHDL, as well as demonstrate an awareness of timing and resource usage associated with each approach.
3. design common sequential functions: flip-flops, registers, latches, and state-machines.
4. create a VDHL test bench and use it to test/verify a sequential VHDL design of moderate complexity.  
5. place, route, and verify timing of a standard cell design.  
6. draw, given commented VHDL code of moderate complexity, a corresponding RTL (Register Transfer Level) block diagram.  
7. use, modify, and create scripts to control the synthesis process.
8. use different design styles, constraints, and optimization options to achieve required synthesis results.
9. explain the difference between various ASIC (Application Specific Integrated Circuit) design approaches - standard cell, full custom, and programmable devices.
10. prepare functional and interface requirements for blocks within a sequential system design.
11. create the hierarchical decomposition of a sequential design.

Engineering Faculty Document No. 2-05

January 17, 2006

Page 3 of 4

12. work in a team and negotiate the division of labor.  
13. gain familiarity with the use and purpose of design reviews.  
14. document the final architecture, design statistics (area, timing), and test results.

Assessment Method for Course Outcomes:

Satisfaction of outcomes i-v, vii, and viii is demonstrated through completion of lab exercises during weeks 7 through 9. Outcomes vi and ix are assessed on written tests. Outcomes x through xiv are satisfied through completion of a final design project.

Engineering Design Content:

Establishment of objectives and criteria: For the final project, students are given a general system specification for which students must define an architecture and specification for individual functional units within the architecture.

Synthesis: Given functional and interface requirements, students use VHDL code to implement a circuit design to satisfy those requirements. Early in the semester, students are provided with detailed specifications for individual blocks. For the final project, students have to conceive of their design RTL (Register Transfer Level) block diagram, and implement and implement each of those blocks.

Analysis: Given a design in either RTL or gate level form, students are required to identify timing delay paths, and prepare timing and area budgets based on their analyses of the design. Results are compared to automated reports which can be extracted from their designs.

Testing and Evaluation: Students practice the development and use of automated or semi-automated test benches for thorough verification of logic designs. These test benches can be applied at each stage of the design process. Note: in industrial practice, ASIC designs are verified extensively by means of simulation and design rule checks because an ASIC fabrication run is extremely expensive and time consuming.

Engineering Design Considerations:

Economic: final projects are required to target either area or timing optimization, both of which have economic implications. Area strongly influences manufacturing cost and

Engineering Faculty Document No. 2-05

January 17, 2006

Page 4 of 4

design yield. Timing strongly influences marketability of many products. Students are also expected to be able to identify and explain implementation alternatives (ASIC, FPGA [Field-Programmable Gate Array], gate array, etc.) appropriate for a particular set of design objectives.

Manufacturability: Design techniques and automated processes practiced in this course are similar to those used in industry to ensure manufacturability.

Lab Outline: