Purdue SoCET
About
The goal of Purdue SoCET (System-on-Chip Extension Technologies) is to provide students hands on experience with a fully developed industry quality SoC design flow. Members of the group engage with architecture exploration, RTL design, physical design, PCB design, chip bringup, verification methods, an array of EDA tools and software development.
Throughout >10 tape-outs completed after a decade, SoCET has grown from 6 to over 350 students involved in the chip design process across different projects: firstly with an ARM CPU, to an open-source RISC-V microcontroller, and expanded our footprint to different projects such as an in-house Graphics Processing Unit, AI Hardware Accelerator and a Datacenter Network Accelerator. This sustained growth reflects SoCET’s strong commitment to developing the next generation of semiconductor talent and helping address the industry’s growing workforce gap.
Recent tape-outs
May 2026, STARS program student designs taped out via ChipFoundry.io. Chips & PCBs received June 2026. Students to receive/test fall 2026.
AFTx08 2026 taped out April 2026 for fabrication on TSMC 180nm process. Dice received June 2026, preparing to package.
AFTx07+ 2024 for fabrication on the Skywater 130nm process.
AFTx07 2024 for fabrication on the Skywater 130nm process.
2022: an experimental design on TSMC 180nm was taped out via MUSE Semiconductor. This IC is a test chip to demonstrate applications of polymorphic logic in logic locking, recongurability, and countermeasures against reverse engineering.
AFTx06 2021 for fabrication on the Skywater 130nm process in connection with the Google sponsored open-source MPW runs as described here.
Announcements
SoCET pre-registration applications are open until the end of September.
Students who are continuing their senior design (i.e. VIP 47921 -> VIP 47922) will be granted priority acceptance. Students who would like to resume their project in the upcoming semester are encouraged to apply as soon as possible.
- You can apply using this Qualtrics Form. Please completely fill it out.
STARS: Chip Design Spring 2027 pre-registration applications are being accepted until September 31st
STARS: Chip Design is a program primarily for first- and second-year students and design to introduce digital design concepts and design flow tools. The first semester is primarily focused on foundational knowledge and project preparation. The second semester uses prior knowledge to conceptualize and implement a semester-long digital project to be implemented in SystemVerilog, tested on FPGAs, and prepped for tapeout (GDSII).
STARS Chip Design Skills/Project
- Student Training Awareness and Readiness for Semiconductors.
- For new SoCET members in their Freshman or Sophomore year.
- First semester - STARS: Chip Design Skills - design and simulation techniques
- Second semester - STARS: Chip Design Project - FPGA prototype & tape-out for fabrication
- Completion of tape-out earns STARS certificate.
GPU Team
- Develop SIMT (Single Instruction, Multiple Threads) GPU targeting graphics and parallel workloads
- Full-stack GPU design following industry standards: workloads, software stack, custom ISA, compiler, architecture, simulation, and RTL
- End-to-end development from applications and kernels down to cycle-accurate models and RTL
- Split into: graphics & software, compilers, hardware architecture & RTL
AI Hardware Team
- Develop AI accelerator for both training and inference
- Full software–hardware stack: PyTorch kernels, system software, compiler, architecture, and RTL
- Focus on performance, efficiency, and scalability through hardware–software co-design
- Split into: system software, compilers, vector core, scheduler, systolic array, scratchpad, and DRAM/memory
Data Center Network Accelerator
- Develop a network accelerator for datacenter and distributed systems workloads.
- Full-stack design: networking stack, software, architecture, and RTL
- Focus on high throughput, low latency, and scalable data movement
Digital Design
- Focuses on the architecture and implementation of RISC-V–based systems and advanced SoC components
- Projects span improvements to the RISC-V CPU core, work on the chip interconnect, and development of digital peripherals.
- Example RISC-V projects: Multi-core processor, multi-core interrupts, RISC-V extensions, branch predictors, DMA, power management
- Example peripheral projects: SPI, PWM, Timer
Verification
- Ensures correctness and reliability of SoC designs
- Focuses on industry standard UVM-based verification and reusable testbenches
- Validates processors, memory systems, and custom hardware blocks
Analog/Mixed Signal
- Focuses on designing non-digital components that bridge real-world signals and on-chip processing
- Enables integration between physical sensors, power systems, communication interfaces, and digital logic
- Example projects: LDO, Op-amp, DAC, Wireless
Software
- Compiler toolchains, IO libraries, RTOS porting, demo applications
Physical Design
- Open-source and commercial synthesis/layout/verification
- Physical verification: power and timing
- Tape-out preparation
PCB/Test
- PCB designs for testing and IC demonstrations
Test Engineering
- DFT, ATPG, and post-silicon validation
Papers
M.C. Johnson. ASSURE Final Report. Aug 2020.
J. Covey, M. C. Johnson – System-on-a-Chip Design as a Platform for Teaching Design and Design Flow Integration, Proceedings of the 2019 on Great Lakes Symposium on VLSI, Tysons Corner, VA, 2019.
J. R, Stevens, J. Skubic, E. Colter, and Dr. M. Swabey. Purdue microbrewer: A microcontroller generator. RISCV Microelectronics Conference 2017, Mar 2017.
J. Skubic, J. R. Stevens, C. Y. Tan, Dr. M. Johnson, and Dr. M. Swabey. Riscv-business: A configurable, extensible risc-v core. RISCV Microelectronics Conference 2017, Mar 2017.
M. A. Swabey and M. C. Johnson. Satisfying ABET criterion using an industrial microelectronic skills incubator. 2015 IEEE International Conference on Microelectronics Systems Education, May 2015.
