Previous AFTx Versions

AFTx06

Flowchart diagram of the AFTx06 chip package

Added features:

  • Add compressed instruction set support (RV32C) to our core.
  • Integrated PLIC interrupt controller
  • On chip SRAM thanks to SRAM macros available for Skywater 130nm open source PDK
  • Added SPI and I2C interfaces
  • Ability to program through JTAG port. Already programmable through UART debugger
  • Integrated with Caravelle test harness required for Google sponsored open-source chip fabrication

Taped out June 2021 for fabrication on Skywater 130nm through the Google sponsored open-source chip fabrication program as described here.

Previous versions of AFTx can be found here.

AFTx05

Photo of the AFTx05 chip package

Goal: AFT-X05 will be our second tape-out to MIT-LL on their 90nm FDSOI process. This design incorporates several features intended for research and demonstration including sparsity optimizations of the RISCV core, polymorphic logic, and electromigration test structures.

Status: This design was taped-out on Feb. 18, 2020.

AFTx04

Flowchart showing how the AFTx04 chip works

Goal: AFTx04 is an implementation of a simple microcontroller based on a RISCV core. It is also or first attempt at fabrication through the MIT Lincoln Labs 90nm FDSOI process.

Status: The dice passed manufacturing test at MIT-LL and packaged ICs were delivered in September 2019. NSWC Crane engineer is helped the team run functional test vectors on an automated tester. Except for some odd behavior by the debugger on reset, all of the design functions as intended.

AFTx03

Flowchart showing how the AFTx03 chip works

Goal: AFT-X03’s main focus was to create an SoC with basic functionality. The only supported peripheral is GPIO. This was the team’s first attempt at on-chip SRAM. The simplicity of the chip allows us to focus on establishing a team design flow before moving onto more complex designs.

Status: A minimal chip bring up was performed but due to choice in package the chip proved to be very difficult to test mount to a PCB and test.

AFTx01/AFTx02

Flowchart showing how the AFTx01/02 chip works

Goal: AFT-X01 and AFT-X02 were the team’s first attempt at designing and taping-out an SoC. Both chips have the same architecture. The bus structure of this chip was adopted by all of our current SoCs.

Status: AFT-X01 had an error in the power distribution and could not successfully be powered up. AFT-X02 was successfully powered on during bring-up. We were able to communicate with the debugger through UART.