Research - Center for Secure Microelectronics Ecosystem - Purdue University

Zero-trust IPs through Interposer-based Integration
PI: Paul Gratz; Co-PIs: Jiang Hu, JV Rajendran
In this work we propose to leverage the advent of interposer-based, 2.5D integration to enable the concept of Zero-trust IP integration. In particular, we will explore novel techniques to show formal proof that IP blocks and the interposer have not been tampered with through a highly flexible and practical version of split-manufacturing we dub 2.5D Logic Redaction. Further we will look at mechanisms to leverage the interposer as a root-of-trust in 2.5D integrated systems, securing those chiplets for which trust cannot be otherwise established. We also will look at the assumed security of eFPGA-based redaction. We will develop an attack to retrieve the hardware IP with only black-box access to a programmed eFPGA, based on the effect of modern electronic design automation (EDA) tools on practical hardware circuits and leverage the observation to guide our attack.

SARI: Security-Aware Reconfigurable Interposer
PI: Michel Kinsy
Under this project efforts, the PI is introducing a novel, reconfigurable on-interposer interconnect which enables user-defined security at runtime, bypassing fab-time attacks. The proposed methodology uses a new active reconfigurable interposer based 2.5-D design approach that enables integration time or user-side, hardware-assisted, security features programming. It decouples the security of the chiplet-based design from the individual chiplet fabrication or provenance, or even the interposer itself. It does this by imbuing the active interposer with reconfigurable fabric that can be programmed at integration and end-use stages to provide hardware root-of-trust security guarantees.

Security Threats and Opportunities in Non-volatile Memory based Hardware Accelerator
PI: Shimeng Yu
We will investigate security vulnerabilities introduced by the non-volatility of weights being persistent in the hardware accelerators. There are two aspects of the threats: one is the data integrity in eNVMs and its robustness to environmental or manipulated changes (e.g. by adversary); the other is the data privacy as the valuable information (e.g. DNN model) is stored in the eNVMs even when the chip is powered off.

Securing the Next-Generation Memory Technology: A Physics-Guided Approach
PI: Mohammad Alam; Co-PI: Saeed Mohammadi; Co-PI: Sumeet Gupta
As classical transistor scaling reaches its limits, the semiconductor industry is adopting next-generation non-volatile memories, including MRAM, FeFET, and RRAM, integrated into 2.5D/3D packages and compute-in-memory architectures. While eliminating traditional SRAM and DRAM power and latency bottlenecks, these technologies introduce an uncharacterized class of physics-driven hardware vulnerabilities across commercial and national security applications. This project systematically investigates four physical attack vectors using TSMC-fabricated test ICs and commercial MRAM chips: external magnetic field manipulation, temperature-dependent data snooping, thermal-hammer time-dependent dielectric breakdown (TDDB), and select-transistor hot-carrier injection (HCI) under realistic operating conditions.

Automated and Optimized Redaction-based Locking and Analysis of Accelerated Aging of MRAM
PI: Joerg Appenzeller; Co:PI: Zhihong Chen; Co:PI: Mark Johnson Subtopic 1) Develop an automated redaction-based locking scheme using simulated annealing to scale NAND-NOR encryption beyond hand designs. A custom standard-cell library will enable Synopsys toolchain integration. New polymorphic gates will encrypt circuits where NAND-NOR fails and integrate with the automated scheme across varied circuit structures and sizes. Subtopic 2) Fabricate a scalable, age-aware MRAM architecture to physically quantify degradation beyond theoretical endurance models. Integrated MTJ canary sensors will use memory as its own sensor without external-sensor PPA penalties, providing early warning. A monitoring scheme will detect attack-induced aging and accurately determine remaining unpowered shelf life.

pSHIELD: Stochasic-MTJ Probabilisic Ising Substrates on Silicon CMOS for Physics-Native Side-Channel Resilience
PI: Haiton Li
pSHIELD develops a probabilistic Ising security substrate integrating CMOS with stochastic magnetic tunnel junctions (sMTJs). Probabilistic bits (p-bits) use stochastic Markov-chain sampling, making intermediate power and switching traces distribution samples. The project targets physics-native side-channel resilience and a randomized-Hamiltonian protocol. It will develop (1) a CMOS+sMTJ testchip using TSMC CMOS with post-CMOS sMTJ integration at Purdue’s Birck Nanotechnology Center with a CSME faculty collaborator, and (2) a calibrated, security-aware STCO framework linking sMTJ properties and CMOS design to Ising compute and side-channel metrics, establishing a platform for downstream CSME application research.

FPGAEcho: Non-Invasive FPGA System Verification using RF/Microwave-based Impedance Analysis
PI: Shahin Tajik
In this project, we propose advanced capabilities for physical verification and assurance of single-board computing systems (SBCS) with FPGA chips across multiple threat levels, spanning compromised SBCS with a kill switch or modified FPGA devices, compromised SBCS with counterfeit FPGAs without countermeasures, and compromised SBCS with a reliability issue. 

Attack-resistant voltage and clocking infrastructure for SoCs
PI: Arijit Raychowdhury
Hardware cryptosystems are vulnerable to attacks from malicious agents through a variety of electrical and physical channels. To protect hardware from such attacks, power and clocking circuits need to be designed for resiliency against side-channel attacks. All these techniques come with very high area and power overhead, often eclipsing the hardware cost of the crypto-engine itself. While this can be an acceptable trade-off in microprocessors, the design space is quite different in mobile and IoT platforms that are severely limited in their power and area budgets. This calls for innovations in protection hardware for crypto-engines that are embedded in such devices. The problem is further exacerbated when we consider new crypto standards that are being developed to meet the demands of the embedded markets.

Deep Learning based Cross-device and Cross-process Side Channel Analysis
PI: Sandip Ray; Co-PI: Swarup Bhunia
In this project, we will focus on optimizing the trace collection process and the impact of each individual trace. This will consist of two main goals, 1) an analysis of cross-device and cross-process side channel similarity; and 2) trace expansion and dataset maximization. We will accomplish these through three tasks: (A) Evaluation of Side Channel Behavior between Devices on the Same Process, (B) Cross-Process Side Channel Analysis, and (C) Trace Utility Maximization.

Low-Overhead Side-Channel Attack Resilient Open-Source Post-Quantum Cryographic Accelerators
PI: Shreyas Sen
The rapid advancement of quantum computing has compromised traditional public key cryptography (PKC), such as RSA. To address these quantum threats, NIST introduced Post-Quantum Cryptography (PQC) standards, including FIPS 203 and 204. Implementing PQC with robust side-channel attack (SCA) resilience is challenging, especially for resource-constrained IoT devices. This project focuses on developing low-overhead PQC cores with strong SCA countermeasures, emphasizing efficiency, low power consumption, and cryptographic flexibility.

Hierarchical Side-channel Leakage Assessment for Post Quantum Cryptographic Accelerators
PI: Patrick Schaumont
This project investigates a simulation-driven methodology for side-channel leakage assessment in Post-Quantum Cryptographic Accelerators. A hierarchical, top-down approach is well suited for the early identification of side-channel leakage sources, particularly during the exploration of countermeasures. The proposed assessment encompasses all modeling levels relevant to programmable SoC designs, extending down to the gate level. The methodology is applied to the Adam’s Bridge open-source implementations, with a focus on ML-DSA (Dilithium). The primary outcomes of the project will include a verified pre-silicon side-channel leakage assessment model for Adam’s Bridge and a proof-of-concept hardware demonstrator IC.

Zero-Trust Hardware Architectures for Confidential AI Computing in Heterogeneous Integrated Systems
PI: Vikram Jain
AI combined with 2.5D/3D chiplet integration increases computing power but creates vulnerabilities in untrusted global supply chains. This project develops a Zero-Trust Hardware Architecture for Confidential AI Computing, including FHE, through three areas: (1) a security-aware interposer detecting active probing via UCIe and providing continuous multi-factor attestation; (2) adaptive side-channel defenses, including dynamic masking and active noise injection in AI accelerators, optimized with ZigZag; and (3) a physically isolated Autonomous Security Manager (ASM) chiplet extending open-source Caliptra with hardware-based policy enforcement.

VEDA: A Unified Pre/Post-Silicon Verification Platform for Quantifiable Assurance
PI: Swarup Bhunia; CoPI: Sandip Ray
In this project, we propose to develop a comprehensive infrastructure, VEDA (Verification based Design Assurance) to address this critical problem. The framework enables trust assessment and verification of a microelectronics device at different stages in its life cycle. VEDA is built to account for zero trust requirements from the ground up, including trust issues in IPs procured from an untrusted IP vendor as well as ICs fabricated by an untrusted foundry and provisioned or tested in an untrusted facility.

Hardware/Software AI Pipeline Security: LLM-Generated RTL and Efficient Secure Edge Inference
PI: Aravind Machiry
AI Accelerators (AIAs) are increasingly integrated into smartphones, IoT, edge, and cloud systems, creating largely unexplored host-system security risks. Current defenses focus on protecting accelerators from malicious hosts, not compromised or misbehaving AIAs, which can enable confused deputy attacks that violate kernel security. This project addresses these threats through three thrusts: (1) threat models and AIABundle, a reproducible dataset of AIA platforms; (2) Multi-level Software Fault Injection (MLSFI) to emulate adversarial AIAs and identify host vulnerabilities; and (3) defenses including OSSR to validate host-resource access and TyPart to isolate accelerator-facing software. It will produce open-source datasets, assessment tools, and defenses for secure AIA integration.