CSME Publications - Center for Secure Microelectronics Ecosystem - Purdue University

CSME is a public-private-academic partnership committed to addressing the complex challenges of securing the global microelectronics supply chain—a matter of critical importance to both economic competitiveness and national security. This archive showcases peer-reviewed and open-sourced publications authored by CSME-affiliated faculty and graduate students from institutions across the U.S., reflecting collaborative research supported by industry and government partners.

This archive features peer-reviewed and open-sourced publications produced through CSME’s research activities. The work showcased here spans trusted hardware design, secure manufacturing practices, system-level assurance, and novel methodologies that reflect a zero-trust approach to microelectronics. CSME’s unique consortium model—guided by a governing council and technical steering committee composed of industry and government partners—enables academic institutions to contribute to solutions that are difficult to achieve through industry or government efforts alone. These publications represent the collective impact of that mission.

Peer-Reviewed Publications

T. Kulkarni, N. Chawla, G. Subbarayan, "Physical Authentication of Electronic Devices using Synthetically Generated 3D Material Signatures" 2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, pp. 955-959 (2023)

Z. Han, M. Shayan, A. Dixit, M. Shihab, Y. Makris, J. Rajendran, “FuncTeller: how well does eFPGA hide functionality?” In Proceedings of the 32nd USENIX Conference on Security Symposium (SEC '23) USENIX Association, USA, Article 325, pp. 5809–5826, (2023)

A. Ghosh, M. A. Rahman, D. Das, S. Ghosh and S. Sen, "Power and EM SCA Resilience in 65nm AES-256 Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits," 2023 IEEE Custom Integrated Circuits Conference (CICC), San Antonio, TX, USA, pp. 1-2 (2023)

M. A. Zaman Mamun, N. J. Conrad, S. Mohammadi and M. A. Alam, "Validating Supply Chain against Recycled COTS ICs using I/O Pad Transistors: A Zero-Area Intrinsic Odometer Approach," 2024 IEEE International Reliability Physics Symposium (IRPS), Grapevine, TX, USA, pp. 01-08 (2024)

G. Chacon, C. Williams, J. Knechtel, O. Sinanoglu, P. Gratz, V. Soteriou, "Coherence Attacks and Countermeasures in Interposer-Based Chiplet Systems", ACM Transactions on Architecture and Code Optimization, Volume 21, Issue 2, Pages 1-25 (2024) 

M. DeLorenzo, V. Gohil and J. Rajendran, "CreativEval: Evaluating Creativity of LLM-Based Hardware Code Generation," 2024 IEEE LLM Aided Design Workshop (LAD), San Jose, CA, USA, pp. 1-5, (2024)

R. Kande, V. Gohil, M. DeLorenzo, C. Chen and J. Rajendran, "LLMs for Hardware Security: Boon or Bane?," 2024 IEEE 42nd VLSI Test Symposium (VTS), Tempe, AZ, USA, pp. 1-4, (2024)

S. Konno, Z. Ellis, A. Golder, S. Ryu, D. Dinu, A. Varna, S. Mathew, A. Raychowdhury "A 65nm Delta-Sigma ADC Based VDD-Variation-Tolerant Power-Side-Channel-Attack Monitor with Detection Capability Down to 0.25Ω," 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, pp. 1-2, (2024)

Y. Ray, A. Ghosh, S. Antal and S. Sen, "A 54μW Design-Agnostic Clock, Voltage, and EM-Pulse Fault-Injection Attack Detection Using Time-to-Voltage Conversion," 2025 IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, 2025, pp. 1-3, doi: 10.1109/CICC63670.2025.10983804.

M. DeLorenzo, K. Tieu and J. Rajendran, "Tracing the Logic: Evaluating LLM Reasoning Paths in RTL Generation," 2025 IEEE 43rd International Conference on Computer Design (ICCD), Richardson, TX, USA, 2025, pp. 776-781, doi: 10.1109/ICCD65941.2025.00115.

J. S. Peterson, S. Gaur, D. Lai, S. Mohammadi and M. A. Alam, "BEOL Resistive Sensors for High Resolution Thermal Fingerprinting," 2026 IEEE International Reliability Physics Symposium (IRPS), Tucson, AZ, USA, 2026, pp. 1-5, doi: 10.1109/IRPS61424.2026.11499314.

M. DeLorenzo, P. Tieu, C. Chen, V. Gohil and J. Rajendran, "Watermarking LLMs — Challenges and Opportunities in Electronic Design Automation," 2025 IEEE International Conference on Omni-layer Intelligent Systems (COINS), Madison, WI, USA, 2025, pp. 1-4, doi: 10.1109/COINS65080.2025.11125763.

K. B. Nine; C. Talley; A. S. Mandadi; T. Krishna; and A. Raychowdhury , “Optimizing Sparse/Dense VEGETA Accelerator Performance with Microscaling Quantization” iscas2025/ESR

K. Raj, A. Chatterjee, P. Slpsk, S. Bhunia, and S. Ray, “ SENTRY: Protecting System-on-Chip Designs against Supply-Chain Attacks. ACM Trans. Embed. Comput. Syst. 25, 3, Article 35 (May 2026), 25 pages. https://doi.org/10.1145/3797869

T. Tabassum, E. Elias, K. Raj, A. Chatterjee, S. Bhunia and S. Ray, "Right-Sized Security: Configurable Security Engine for Supply-Chain Integrity in Resource-Constrained System-on-Chip Designs," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, doi: 10.1109/TVLSI.2026.3693611.

X. Chen, M. Merugu, J. Zhang, and S. Ray, “AroMa: Evaluating Deep Learning Systems for Stealthy Integrity Attacks on Multi-tenant Accelerators”  J. Emerg. Technol. Comput. Syst. 19, 2, Article 13 (April 2023), 17 pages.

H. Rahaman, A. Chatterjee and S. Bhunia, "SAMURAI: Runtime Attack Detection in AI Accelerators Using AI Performance Counters," in IEEE Transactions on Circuits and Systems for Artificial Intelligence, doi: 10.1109/TCASAI.2026.3674059.

S. Paria, A. Dasgupta, D. R. Ankireddy, P. Chakraborty and S. Bhunia, "FV-PAL: Scalable Formal Verification through Partitioning and LLM-Guided Property Generation," 2025 IEEE 43rd International Conference on Computer Design (ICCD), Richardson, TX, USA, 2025, pp. 768-775, doi: 10.1109/ICCD65941.2025.00114.

M. Hasan, S. Paria, S. Bhunia and T. Hoque, "COVERT: Trojan Detection in COTS Hardware via Statistical Activation of Microarchitectural Events," 2026 Design, Automation & Test in Europe Conference (DATE), Verona, Italy, 2026, pp. 1-7, doi: 10.23919/DATE69613.2026.11539495.

J. Yang, A. Ghosh, D. Das and S. Sen, "Analysis of Shunt LDO With Physical Security to Power/EM Side-Channel Attacks," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 73, no. 6, pp. 3939-3952, June 2026, doi: 10.1109/TCSI.2026.3659934

A. Roy, P. G. Malettira, M. Nagaraj, K. Roy “TopoCore: Unifying Topology Manifolds and Persistent Homology for Data Pruning”  neurips.cc/virtual/2025/loc/san-diego/136831

K. M. Islam, E. Elias, D. Das, B. Chatterjee and S. Ray, "Logic Infusion: Exploiting Topology as a Power Side-Channel Countermeasure in FPGA-Based AES," 2026 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Washington, DC, USA, 2026, pp. 438-448, doi: 10.1109/HOST68814.2026.11604599.

P. Kiaei & P.  Schaumont, “SoC Root Canal!: Root Cause Analysis of Power Side-Channel Leakage in System-on-Chip Designs”  IACR Transactions on Cryptographic Hardware and Embedded Systems. 751-773. 10.46586/tches.v2022.i4.751-773.

Open-Sourced Publications

V. Gohil, M. DeLorenzo, V. Nallam, J. See, J. Rajendran “LLMPirate: LLMs for Black-box Hardware IP Piracy,” arXiv: 2411.16111 (2024) – Accepted by NDSS Symposium 2025

M. DeLorenzo, A. Chowdhury, V. Gohil, S. Thakur, R. Karri, S. Garg, J. Rajendran “Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS,” arXiv: 2402.03289 (2024)

A. Roy, K. Roy “DCT-CryptoNets: Scaling Private Inference in the Frequency Domain,” arXiv: 2408.15231 (2024) – Accepted by ICLR 2025

J. Gammell, A. Raghunathan, K. Roy “Power side-channel leakage localization through adversarial training of deep neural networks,” arXiv: 2410.22425

S. Kundu, A. Ghosh, A. Karmakar, S. Sen, I. Verbauwhede, “Rudraksh: A compact and lightweight post-quantum key-encapsulation mechanism,” arXiv: 2501.1379

J. Gammell, A. Raghunathan, A. Hashemi, K. Roy, “Learning to localize leakage of cryptographic keys through power consumption” arXiv: 2503.07464

S. Bush, M. DeLorenzo, P. Tieu, J. Rajendran, “Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMs” arXiv: 2505.06096

J. Read, M. Lee, W. Huang, Y. Luo, A. Lu, S. Yu, “NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealities” arXiv: 2505.02314

Joshua Mashburn, Johann Knechtel, Florian Klemme, Hussam Amrouch, Ozgur Sinanoglu, Paul Gratz, “TWA: Targeted Wearout Attacks in Microprocessor Cores” arvix: 2508.16868

M DeLorenzo, P. Tieu, P. Jana, P., D. Kalathil, V. Ganesh, J. Rajendran, “Abstraction-of-Thought: Intermediate Representations for LLM Reasoning in Hardware Design”  arvix: 2505.15873

M. Merrell, D. Puckett, G. Chacon, J. Stuecheli, S. Kalafatis, P. Gratz “ORAP: Optimized Row Access Prefetching for Rowhammer-mitigated Memories” arvix 2602.13434

M.Merrell, L. Wang, P. Gratz, S. Kalafatis “ SPPAM: Signature Pattern Prediction and Access-Map Prefetcher” arvix 2602.04100

D. Shanmugam, Z. Liu, P. Schaumont “Open-Source Reference for Reproducible Side-Channel Assessment of Post-Quantum Standards” Open source reference