Current Projects

A.   Compute-in-Memory using CMOS SRAM and DRAM Arrays

B.  Spin-based devices and Memristive crossbars as in-Memory Computing Primitives

C.   ROM-Embedded RAM Structures in SRAM and STT-MRAM and their adoption to Accelerate Neuromorphic Applications

A.   Stochastic Neural Networks

With the increasing availability of compute power, state of the art CNNs are growing rapidly in size, making them prohibitive to deploy in power-constrained environments. To enable ubiquitous use of deep learning techniques, we are looking into techniques that reduce the size of a model with minimal degradation in accuracy. Some of the algorithmic techniques we have devised to tackle this include identifying redundancy among the weights of a model in a single shot, discretized leaning and inference methods, and strategies that change network architecture to enable efficient inference. We have also developed hardware driven approximation methods that leverage the inherent error resilience of CNNs for model compression.

Recent Publications:

1. Garg, Isha, Priyadarshini Panda, and Kaushik Roy. "A low effort approach to structured CNN design using PCA." arXiv preprint arXiv:1812.06224 (2018).
2. Panda, Priyadarshini, Abhronil Sengupta, and Kaushik Roy. "Conditional deep learning for energy-efficient and enhanced pattern recognition." 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2016.
3. Chakraborty, Indranil, et al. "PCA-driven Hybrid network design for enabling Intelligence at the Edge." arXiv preprint arXiv:1906.01493 (2019).
4. P. Panda, A. Ankit, P. Wijesinghe, and K. Roy, “FALCON: Feature Driven Selective Classification for Energy-Efficient Image Recognition,” IEEE Transactions on CAD, 2016.
5. Sarwar, et al. "Energy-efficient neural computing with approximate multipliers." ACM Journal on Emerging Technologies in Computing Systems (JETC) 14.2 (2018): 16.

Current Students: Jason Allred, Aayush Ankit, Indranil Chakraborty, Isha Garg, Deboleena Roy

The ability to maliciously perturb any input to a deep learning model and cause a misclassification with high confidence belies a lack of security and credibility to what the models have learned. We are working on methods that explain why adversarial attacks occur, and how we can make models more robust to them.

Recent Publications:

1. Panda, Priyadarshini, and Kaushik Roy. "Explainable learning: Implicit generative modelling during training for adversarial robustness." arXiv preprint arXiv:1807.02188 (2018). 
2. Sharmin, Saima, et al. "A Comprehensive Analysis on Adversarial Robustness of Spiking Neural Networks." IJCNN 2019.
3. Panda, Priyadarshini, Indranil Chakraborty, and Kaushik Roy. "Discretization based Solutions for Secure Machine Learning against Adversarial Attacks." IEEE Access (2019).

Current Students: Indranil Chakraborty, Chankyu Lee, Wachirawit Ponghiran, Saima Sharmin 

The capacity to learn new things without forgetting already present knowledge is innate to humans. However, all neural networks suffer from the problem of catastrophic forgetting, making it hard to grow networks and learn newer incoming data in a fluid manner. We are exploring techniques that utilize stochasticity or architectural enhancements that can enable lifelong learning.

Recent Publications:

1. Allred, Jason M., and Kaushik Roy. "Stimulating STDP to Exploit Locality for Lifelong Learning without Catastrophic Forgetting." arXiv preprint arXiv:1902.03187 (2019).
2. Roy, Deboleena, Priyadarshini Panda, and Kaushik Roy. "Tree-CNN: A hierarchical deep convolutional neural network for incremental learning." arXiv preprint arXiv:1802.05800 (2018).
3. Panda, Priyadarshini, et al. "Asp: Learning to forget with adaptive synaptic plasticity in spiking neural networks." IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8.1 (2017): 51-64.
4. Sarwar, Syed Shakib, Aayush Ankit, and Kaushik Roy. "Incremental learning in deep convolutional neural networks using partial network sharing." arXiv preprint arXiv:1712.02719 (2017).

Current Students: Aayush Ankit, Jason Allred, Deboleena Roy

‘In-Memory computing’ is a promising candidate to achieve significant throughput and energy benefits. Currently, we are exploring novel ideas to incorporate compute capabilities inside SRAM and DRAM. We have shown that digital bulk-bitwise/arithmetic operations and analog binary/multi-bit dot-product computations/ multiplication can be performed inside SRAM arrays. Moreover, in-memory full addition has been shown using commodity DRAM banks. Currently, we are exploring different methodologies to add compute functionalities in embedded DRAM gain cells. We run neuromorphic/machine learning applications (e.g. ANNs, SNNs, k-NN) on such in-memory computing based systems to evaluate performance and energy benefits against conventional von Neumann systems.

Recent Publications:

1. Agrawal, A. Jaiswal, B. Han, G. Srinivasan, and K. Roy, “Xcel-ram: Accelerating binary neural networks in high-throughput SRAM compute arrays,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 8, pp. 3064-3076, Aug. 2019.
2. A. Jaiswal, I. Chakraborty, A. Agrawal, and K. Roy, “8t sram cell as a multi-bit dot product engine for beyond von-neumann computing,” arXiv preprint arXiv:1802.08601, 2018.
3. A. Agrawal, A. Jaiswal, C. Lee, and K. Roy, “X-sram: Enabling inmemory boolean computations in cmos static random access memories,” IEEE Transactions on Circuits and Systems I: Regular Papers, no. 99, pp. 1–14, 2018.

Current Students: Amogh Agrawal, Mustafa Ali, Sangamesh Kodge

C.   ROM-Embedded RAM Structures in SRAM and STT-MRAM and their adoption to Accelerate Neuromorphic Applications

Embedding ROM storage in RAM arrays provides an almost cost-free opportunity to perform transcendental functions and other lookup-table (LUT) based computations in memory. We have developed RAM arrays with the ability to store ROM data in the same array using different memory technologies like CMOS SRAM and STT-MRAM. Moreover, we adopt such ROM-embedded RAM structures in accelerator architectures to accelerate Neuromorphic applications that depend heavily on such LUT-based operations.

Recent Publications:

1. A. Agrawal, A. Ankit and K. Roy, "SPARE: Spiking Neural Network Acceleration Using ROM-Embedded RAMs as In-Memory-Computation Primitives," in IEEE Transactions on Computers, vol. 68, no. 8, pp. 1190-1200, 1 Aug. 2019.
2. A. Agrawal and K. Roy, "RECache: ROM-Embedded 8-Transistor SRAM Caches for Efficient Neural Computing," 2018 IEEE International Workshop on Signal Processing Systems (SiPS), Cape Town, 2018, pp. 19-24.
3. X. Fong, R. Venkatesan, D. Lee, A. Raghunathan and K. Roy, "Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 24, no. 3, pp. 992-1002, March 2016.
4. D. Lee and K. Roy, "Area Efficient ROM-Embedded SRAM Cache," in IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, vol. 21, no. 9, pp. 1583-1595, Sept. 2013.
5. D. Lee, X. Fong, and K. Roy, “R-MRAM: A ROM-Embedded STT MRAM Cache,” IEEE Electron Device Letters 34 (10), 1256-1258, 2013.

Current Students: Amogh Agrawal

A.   Stochastic Neural Networks

We proposed stochastic Spiking Neural Networks (SNNs), realized using MTJ as stochastic spiking neurons that switch probabilistically based on the input, wherein the binary weights are trained offline using error backpropagation. In addition, we proposed SNNs composed of stochastic binary weights trained using hardware friendly Spike Timing Dependent Plasticity (STDP) based probabilistic learning algorithm, which can be enabled by MTJ-based synaptic crossbar arrays with high energy barrier to realize state-compressed hardware with on-chip learning capability. Advantageously, use of high energy barrier MTJ (30-40KT where K is the Boltzmann constant and T is the operating temperature) not only allows compact stochastic primitives, but also enables the same device to be used as a stable memory element meeting the data retention requirement. Such stochastic MTJ-based realization can be potentially an order of magnitude energy-efficient compared to CMOS-only implementations.

Recent Publications:

1. Srinivasan, G., Sengupta, A. and Roy, K. "Magnetic tunnel junction based long-term short-term stochastic synapse for a spiking neural network with on-chip STDP learning," Scientific Reports, 6, p.29545, 2016.
2. Sengupta A., Panda, P, Wijesinghe P., Kim Y., and Roy, K., “Magnetic Tunnel Junction Mimics Stochastic Cortical Spiking Neurons,” Scientific Reports, 6, p. 30039, 2016.
3. Srinivasan, G. and Roy, K. "ReStoCNet: Residual Stochastic Binary Convolutional Spiking Neural Network for Memory-Efficient Neuromorphic Computing," Frontiers in Neuroscience, 13, p.189, 2019.
4. Sengupta, A., Srinivasan, G., Roy, D. and Roy, K. "Stochastic inference and learning enabled by magnetic tunnel junctions," In 2018 IEEE International Electron Devices Meeting (IEDM), p. 5-6, IEEE, December 2018.
5. Sengupta, A., Parsa, M., Han, B. and Roy, K. "Probabilistic deep spiking neural systems enabled by magnetic tunnel junction," IEEE Transactions on Electron Devices, 63(7), pp.2963-2970, 2016.
6. Liyanagedera, C.M., Sengupta, A., Jaiswal, A. and Roy, K. "Stochastic spiking neural networks enabled by magnetic tunnel junctions: From nontelegraphic to telegraphic switching regimes," Physical Review Applied, 8(6), p.064017, 2017.

Current Students: Bing Han, Chamika Liyanagedera, Maryam Parsa, Deboleena Roy, Gopal Srinivasan