UPWARDS Network - Semiconductors - Purdue University

A set of courses have been developed and recorded. They are Introduction to "Data Analytics, Design of Experiments, and Machine Learning" and "Reliability Physics of Advanced Packaging." A new VR-based module for memory fabrication is being developed (see the following section for more detail).

The UPWARDS Purdue team had an open call for proposals on curriculum development and experiential learning in May, 2024. The following two projects were selected, and they are being developed.

• Project Title: Emerge: Exploring Memory Education via Realistic Generated Experiences

  PIs: Prof. Mustafa Hussain and Prof. Dimitrios Peroulis - Purdue ECE

  vFabLab is an innovative virtual platform providing in-depth, interactive training on semiconductor device fabrication. Accessible worldwide, it has trained over 1,700 students from 540+ institutions, effectively preparing them for cleanroom operations. This project aims to enhance vFabLab by integrating 3D headset compatibility and offering specialized training on memory device fabrication, including SRAM, DRAM, and non-volatile memory. The platform's objectives include democratizing access to high-quality semiconductor education and fostering a global community for collaboration and lifelong learning. The objectives are multifaceted: 1. Comprehensive Training: Deliver in-depth training modules covering the fabrication processes of diverse memory devices. 2. Skill Enhancement: Provide practical experience in memory device fabrication through virtual simulations. 3. Specialized Focus: Tailor training modules to address the specific intricacies of different memory device types. 4. Global Accessibility: Make vFabLab accessible worldwide, democratizing access to high-quality training resources. 5. Continuous Improvement: Enhance vFabLab's capabilities based on user feedback and industry advancements.

• Project Title: 2D-FeFET Embedded DRAM for On-Chip DNN Training with Floating-Point Compute-In-Memory Design

  PIs: Prof. Haitong Li (Purdue), Prof. Joerg Appenzeller (Purdue), Prof. Akinobu Teramoto (Hiroshima University), Prof. Haruka Suzuki (Nagoya University), Prof. Zhihong Chen (Purdue)

  The team proposes a co-designed 2D-material ferroelectric FET (2D-FeFET) based embedded DRAM (eDRAM) solution for memory-centric AI hardware, specifically for on-chip DNN training with floating-point precisions. Utilizing transition metal dichalcogenides (TMDs) as high-performance channels and a ferroelectric gate stack in a 2-T gain-cell structure, we aim to achieve scalable CIM operations. This project covers material characterization, memory-centric computing, and experiential learning. The proposed design promises significant energy savings compared to advanced CMOS accelerators, with plans for hands-on student training and international collaboration. In Experiential Learning thrust, specifically, based on the proposed co-design drivers, the team will launch a new course project in the Purdue VIP course, Semiconductors@ Birck, providing hands-on nanofabrication and characterization experience to undergraduate students. A Purdue-Hiroshima-Nagoya joint workshop will also be held, and student exchange visits will be organized.

Purdue will fund four Ei-ichi Negishi fellowships, to further develop curriculum and R&D in areas of interest to the UPWARDS program. (Dr. Negishi: Japanese-American, Purdue faculty, 2010 Nobel Prize recipient in Chemistry).

The UPWARDS program has appointed 12 women faculty (UPWARDS faculty), promoting research opportunities, diversity and nurturing future talent. It has also reached 780 female students through events and classes, such as "Inclusive Society" and "My Dream for Engineering".

1. Appointment of UPWARDS Faculty

   Dan Jiao was selected as Purdue's UPWARDS PI (Industry). She is the Synopsys Professor in Purdue University's Elmore Family School of Electrical and Computer Engineering. She directs Rapid-HI (Heterogeneous Integration) Design Institute, an Elmore ECE Emerging Frontiers Center. A fellow of the IEEE and a Distinguished Microwave Lecturer of the IEEE MTT Society, Jiao has authored over 350 papers in refereed journals and international conferences. Her research has been recognized by the 2022 Computational Electromagnetics Award of the ACES society, the 2019 Intel's Outstanding Researcher Award, the 2013 Sergei A. Schelkunoff Prize Paper Award of the IEEE Antennas and Propagation Society (AP-S), numerous Best Paper Awards and Finalists in conferences. She was one of 85 selected for the National Academy of Engineering's (NAE) 2011 U.S. Frontiers of Engineering Symposium, a recipient of the NSF Career Award in 2008, the Intel Logic Technology Development Divisional Achievement Award in 2003, and the 2000 Raj Mittra Outstanding Research Award. She has been appointed the editor-in-chief of the IEEE Journal on Multiscale and Multiphysics Computational Techniques.

2. Summer camp for women.

   Tokyo Electron organized an exciting summer program: "UPWARDS Summer Camp for Women".

   This is a program for female students at universities participating in UPWARDS. "Staying at 'Tokyo Electron Karuizawa Club' in Nagano, students can learn about everything from semiconductors to Tokyo Electron while enjoying some fun activities!"

   • Held: Aug 20 through Aug 22

     Enrollment: 1 to 3 students per university

   More information about this program (Japanese & English)

3. Women researchers and students in semiconductors.

   Prof. Shubhra Bansal's research project titled "Electro- and Thermo-migration Analysis of Cu-pillar Assembly at sub-10 micron Pitch" has been selected for funding by Purdue's UPWARDS program. Three female students have also been recruited into the UPWARDS research program.

   Our "Semiconductors in Japan" study abroad program held from May 5 to May 18 in Japan has 18% female students.

The experiential learning has been integrated into multiple other pillars of the UPWARDS program.

Integration with Pillar 5 (exchange program): In Hiroshima University's visit to Purdue from Feb. 24 to March 5, 2024, students visited Purdue's Birck Nanotechnology Center, attended technical lectures, participated in CHIPS seminar with ~100 students, and visited local companies and cultural events. In Purdue students' visit to Japan in May 2024, students visited the Center for Innovative Integrated Electronic Systems (CIES) at Tohuku University and listened to lectures related to semiconductors.

Integration with Pillar 4 and Pillar 1 (research and curriculum program): Undergraduate and graduate students are involved in the four research and education programs funded by UPWARDS. They have gained hands-on experiences and received comprehensive training on various memory device fabrication processes, including SRAM, DRAM, and non-volatile memory.

Purdue hosted three faculty-led workshops for the faculty from Hiroshima and Tohoku universities. This allowed the groups to harmonize research and teaching plans.

The UPWARDS Purdue team had an open call for proposals on collaborative research in May, 2024. The following three research projects were selected.

1. Project Title: Full 3D thermal map reconstruction of commercial processing-in-memory 3D stacks

   PIs: Prof. Peter Bermel (Purdue), Prof. Seiichiro Higashi (Hiroshima University), David Guzman (Micron Technology)

   This project explores the potential of Processing-in-Memory (PIM) technologies using 3D stacks like high-bandwidth memory (HBM) to enhance performance by reducing power consumption and latency. The increased thermal load from PIM poses significant thermal management challenges, which this research addresses through advanced thermometry and thermo reflectance imaging techniques. By combining experimental data with 3D thermal modeling, the project aims to create a detailed thermal map of a PIM/HBM stack, identifying hot spots and failure risks. Additionally, it supports workforce development through a new course and industry internships for students.

   Publication. Lee, Changkyun, Jiawei Song, Haiyan Wang, Jie Zhu, Vidisha Singhal, and Peter Bermel. "Temperature-dependent optical dispersion of composite oxide multilayers." In Nonimaging Optics: Efficient Design for Illumination and Concentration XIX, p. PC1313207. SPIE, 2024.

2. Project Title: Electro- and Thermo-migration Analysis of Cu-pillar Assembly at sub-10 micron Pitch

   PI: Prof. Shubhra Bansal (Purdue)

   This project focuses on advancing Cu-pillar hybrid bonding technology to meet the demands of high-performance memory and computing, particularly for the 1 nm Silicon Node. The research evaluates the thermo-migration and electromigration reliability of Cu-pillar thermo-compression bonding with low-temperature solder for chip-to-package interconnections at a 5 µm bump pitch. The study combines modeling and experimental approaches to assess bond strength, void formation, and electromigration resistance. Additionally, it supports the development of a 9-credit concentration in Heterogeneous Integration & Advanced Packaging as part of the DOD SCALE program.

3. Project Title: 2D-FeFET Embedded DRAM for On-Chip DNN Training with Floating-Point Compute-In-Memory Design

   PIs: Prof. Haitong Li (Purdue), Prof. Joerg Appenzeller (Purdue), Prof. Akinobu Teramoto (Hiroshima University), Prof. Haruka Suzuki (Nagoya University), Prof. Zhihong Chen (Purdue)

   Emerging memory-intensive applications, including the secure fine-tuning of large language models for downstream tasks in edge devices (autonomous vehicles, robots, AR/VR), are steering the advancement of memory-centric AI hardware towards on-chip DNN training with floating-point precisions. Incumbent memory technologies and inference accelerators fall short of meeting these demands. The team proposes a co-designed 2D-material ferroelectric FET (2D-FeFET) based embedded DRAM (eDRAM) solution for memory-centric AI hardware, specifically for on-chip DNN training with floating-point precisions. Utilizing transition metal dichalcogenides (TMDs) as high-performance channels and a ferroelectric gate stack in a 2-T gain-cell structure, the team aim to achieve scalable CIM operations. This project covers material characterization, memory-centric computing, and experiential learning. In Material Characterization thrust, experimental 2D-TMD material characterizations will be performed with ferroelectric gate stacks and fabricate/optimize 2-T eDRAM primitives employing 2D-FeFETs. Key technology specs of the hybrid eDRAM will be characterized for benchmarking. In Memory-Centric Computing thrust, the team will experimentally demonstrate precision-scalable CIM operations on the developed platform, with 2 x 2 array prototypes to be fabricated. Calibrated with electrical measurements, an architecture simulator with CIM circuits will be built to enable cross-layer design space explorations for FP-training and INT-inference. To collectively identify future optimizations, Dr. Teramoto (Hiroshima Univ) will conduct surface analysis (XPS/XRD/AFM) using Purdue's devices, and Dr. Suzuki (Nagoya Univ) will explore plasma etching/deposition.

   • Publication: L. Zheng and H. Li, "CMOS+X Technologies for Neuro-Vector-Symbolic Computing," Device Research Conference (DRC), June 2024.
   • Dr. Li organized a special session at ICCAD 2024 on edge AI and role of emerging memories
   • Dr. Li gave an invited talk at ESWEEK 2024 on memory-centric computing.

1. First Japanese partner visit: Hiroshima University visit to Purdue, Feb. 24 - Mar. 5, 2024.

   Purdue hosted a short-term academic visit for nine diverse Hiroshima University students led by Ms. Kaori Taka, Chief of Global Initiatives Group, International Office at Hiroshima University and Dr. Taiji Hotta, Vice-Executive Director of Super Global University (SGU) Project, Director of the Office of Global Initiative, Hiroshima University, and Professor, Center for the Study of International Cooperation in Education (CICE), the IDEC Institute. The visit program incorporated lab visits, technical lectures, local company visits (e.g., Subaru) and cultural visits.

   Hiroshima University welcome reception was held on Feb. 26, 2024 (see photo below), where Hiroshima students and program leaders met with Purdue leadership and student mentors during their first day of campus activities.

   

2. Purdue UPWARDS Study Abroad program, "Semiconductors in Japan," held May 5 to May 18, 2024.

   The program was led by Purdue University's Vice President Cristina Farmus and George Chiu, assistant dean for Global Engineering Programs and professor of mechanical engineering. Twenty-two Purdue undergraduate students visited Japan to learn more about the semiconductor industry and technical advancements. They visited universities and companies that are part of the UPWARDS network, including Tokyo University, Tohoku University, Hiroshima University, Tokyo Electron Company and Micron, among other relevant visits. They also listened to lectures related to semiconductors.

   Visit the following link for more info:

   https://web.tohoku.ac.jp/ged/12430?lang=en

   

3. Purdue First-Year-Engineering study abroad program "Global Design and Practice for Pre-engineering in Taiwan and Japan."

   Participants visited Japan from June 15-30, 2024. They visited world-class semiconductor companies as well as UPWARDS university partners, like Tohoku University. The program has yielded 40% female participation historically.

   

Shubhra Bansal, Principal Investigator

Associate Professor of Mechanical Engineering and Materials Engineering

As the demand for high performance computing increases, interconnect and die attach materials are needed to meet the requirements of 0.5 µm line width, sub-10 µm bump pitch, high I/O density, and power density for 1 nm Silicon Node and beyond. Cu-pillar technology with hybrid bonding has achieved sub-5 µm bump pitch posing several benefits such as increased I/O density, increased bandwidth, improved 3D stacking, enhanced power efficiency, and reduced parasitics and thermal resistance attributed to the absence of underfill. Although wafer-to-wafer (W2W) hybrid bonding can achieve 50 nm alignment accuracy; thermal budget, reliability, and chip-to-substrate hybrid bonding remain as drawbacks of this technology. In this study, thermo-migration, and electromigration reliability of Cu-pillar thermo-compression bonding via low-temperature solder will be evaluated for chip-to-package interconnections at 5 µm bump pitch. Reliability will be evaluated using combined modeling and characterization approach for thermo-mechanical and electromigration failures for Cu-In, Cu-Sn-Ag and Cu-Sn-Bi material systems through test structure evaluations. Daisy chain Cu- pillars with sub-10 µm pitch and planar serpentine test structures will be used to measure evolution of bond strength, void nucleation, and growth due to vacancy or atomic migration due to thermal, stress, concentration gradients, and electron wind. Electromigration testing will be conducted at temperature under constant current density to measure changes in resistance as a function of time and bond strength will be tested using micro-shear tests with 1 µm resolution. Interfacial void growth, solder voiding and shear strength of Cu-pillar interconnects will be evaluated as a function of temperature, current density, barrier and capping layers, and current crowding at corners. Void growth will be correlated to adhesion strength. Electro- and thermomigration test structures have been designed using finite element model and 1D physics-based electromigration model based in COMSOL. Vacancy profiles, hydrostatic and Von-Mises stress distribution profiles will be modeled to estimate the void nucleation and void growth time as a function of aspect ratio, curvature, temperature, current density, and residual stress. PI is developing 9-credit concentration in Heterogeneous Integration & Advanced Packaging with DOD SCALE program. PI will work collaborate with other UPWARDS faculty to contribute to the HIAP concentration.

Peter Bermel, Principal Investigator

Elmore Professor of Electrical and Computer Engineering

Associate Director of Graduate Admissions

Seiichiro Higashi, Co-PI, Hiroshima University

David Guzman, external partner, Micron

Processing-in-memory (PIM) technologies using 3D stacks, such as high-bandwidth memory, have enormous potential to improve performance by reducing power consumption and latency associated with memory transfer between memory and logic chips. At the same time, the increased thermal load associated with PIM creates an increased thermal management challenge that must be fully understood through improved characterization method. In this work, we leverage prior work from both the Higashi group on optical interference contactless thermometry with Bermel group's publications on thermoreflectance imaging in semiconductor devices to obtain a high-frame rate video of multiple surfaces of a commercially-relevant 3D PIM/HBM stack under various test conditions. To support the development of relevant student expertise suitable for the workforce, a dual-level undergraduate/graduate course will be created to provide an introduction to the thermal, mechanical and electrical drivers of operation and failure in these systems, which will build off of the SCALE program heterogeneous integration/advanced packaging course started by Prof. Ganesh Subbarayan. To further promote workforce development, students will be encouraged after taking the course to perform internships at Micron, and graduate students will be part of a short-term pair of collaborative research visits across the two campuses.

Muhammad Hussain, Principal Investigator

Professor of Electrical and Computer Engineering

Dimitros Peroulis, Co-PI

Senior Vice President for Partnerships and Online

Reilly Professor of Electrical and Computer Engineering

vFabLab stands at the forefront of innovation in semiconductor education, offering a cutting-edge virtual platform accessible from any computer or mobile device. This groundbreaking app provides in-depth interactive training on semiconductor device fabrication processes and equipment, meticulously preparing individuals for the intricacies of cleanroom operations. Under the guidance of Professor Muhammad Hussain at Purdue University, more than 1,700 students from 540+ institutions all over the world have seamlessly transitioned from virtual simulations to real-world semiconductor fabrication, demonstrating the app's effectiveness. By offering step-by-step guidance and an immersive learning environment, vFabLab ensures that users are well-prepared and confident when navigating physical cleanroom facilities. Our proposal aims to leverage vFabLab, including integration with 3D headsets for enhanced immersion, to provide comprehensive training on various memory device fabrication processes, including SRAM, DRAM, and non-volatile memory. Objectives: 1. Comprehensive Training: Deliver in-depth training modules covering the fabrication processes of diverse memory devices. 2. Skill Enhancement: Provide practical experience in memory device fabrication through virtual simulations. 3. Specialized Focus: Tailor training modules to address the specific intricacies of different memory device types. 4. Global Accessibility: Make vFabLab accessible worldwide, democratizing access to high-quality training resources. 5. Continuous Improvement: Enhance vFabLab's capabilities based on user feedback and industry advancements. Methodology: 1. Curriculum Development: Collaborate with experts to develop comprehensive training modules. 2. Interactive Learning: Implement interactive features to facilitate engagement and learning. 3. Assessment and Certification: Develop assessment criteria and offer certifications to validate learners' skills. 4. Community Engagement: Foster an online community for knowledge sharing and collaboration. Expected Outcomes: 1. Empower learners for careers in semiconductor fabrication. 2. Inspire innovation in memory device fabrication. 3. Democratize access to semiconductor education. 4. Cultivate a culture of lifelong learning among semiconductor professionals. 5. Facilitate collaboration between academia, industry, and research institutions. By harnessing vFabLab's capabilities, we aim to revolutionize memory device fabrication training.

Haitong Li, Principal Investigator

Assistant Professor of Electrical and Computer Engineering

Joerg Appenzeller, Co-PI

Barry M. and Patricia L. Epstein Professor of Electrical Engineering

Zhihong Chen, Co-PI

Reilly Professor of Electrical and Computer Engineering

Mary Jo and Robert L. Kirk Director of Birck Nanotechnology Center

Akinobu Teramoto, external partner, Hiroshima University

Haruka Suzuki, external partner, Nagoya University

Emerging memory-intensive applications, including the secure fine-tuning of large language models for downstream tasks in edge devices (autonomous vehicles, robots, AR/VR), are steering the advancement of memory-centric AI hardware towards on-chip DNN training with floating-point precisions. Incumbent memory technologies and inference accelerators fall short of meeting these demands. Our team proposes a co-designed, 2D-material ferroelectric FET (2D-FeFET) based embedded DRAM (eDRAM) solution, capable of floating-point multiply-accumulate (MAC) for on-chip DNN training. We propose to combine transition metal dichalcogenides (TMDs) as the high-performance, low-leakage channels with a ferroelectric gate stack (HZO) in a 2-T gain-cell (GC) structure (Fig. 1a). Based on the hybrid eDRAM reconfigurable between non-volatile and charge-based mode, we devise a novel three-vector-MAC operator to realize floating-point (FP) and integer (INT) analog MACs as compute-in-memory (CIM) primitives. We cover three UPWARDS focus areas as follows. In Material Characterization thrust, building upon our 2D-TMD works (Fig. 1b), we will perform experimental 2D-TMD material characterizations with ferroelectric gate stacks, and fabricate/optimize 2-T eDRAM primitives employing 2D-FeFETs. Key technology specs of the hybrid eDRAM will be characterized for benchmarking. In Memory-Centric Computing thrust, we will experimentally demonstrate precision-scalable CIM operations on the developed platform, with 2 x 2 array prototypes to be fabricated. Calibrated with electrical measurements, an architecture simulator with CIM circuits will be built to enable cross-layer design space explorations for FP-training and INT-inference (Fig. 1c). With the BERT-Base transformer benchmark, the projected energy/token of our design can achieve 3.79 uJ/token (INT8) to 41.69 uJ/token (FP16), a 11X~78X reduction over advanced CMOS accelerators. To collectively identify future optimizations, Dr. Teramoto (Hiroshima Univ) will conduct surface analysis (XPS/XRD/AFM) using our devices, and Dr. Suzuki (Nagoya Univ) will explore plasma etching/deposition. In Experiential Learning thrust, based on our proposed co-design drivers, we will launch a new course project in the Purdue VIP course, Semiconductors @ Birck, providing hands-on nanofabrication and characterization experience to undergraduate students. Finally, we will hold a Purdue-Hiroshima-Nagoya joint workshop and organize student exchange visits.