Samarth Agarwal

Design ideas for Tunnel-FETs

Design ideas for Tunnel-FETs Samarth Agarwal, Mathieu Luisier and Gerhard Klimeck

Objective:

  • To explore design ideas for voltage scaling of transistors.

Approach:

  • VDD scaling : Difficult in MOSFETs, possible in TFETs.
  • gFET: Larger tunneling area gives higher ION than conventional TFETs.
  • Modified and optimized gFET design to meet ITRS requirements.

Impact:

  • gFET with high ION and low IOFF will provide a viable alternative for VDD scaling to reduce power consumption.

Powerpoint slide as ppt, pdf, or as image below.

Samarth Agarwal's Pages

Biography Effective band-gaps of a superlattice Design ideas for Tunnel-FETs Adaptive Quadrature for Sharply Spiked Integrands Quantum transport in Resonant Tunneling Diodes(NEGF based) Poisson Schrodinger Solver for 1D heterostructures Piecewise Constant Potential Barrier Tool