Samarth Agarwal

Design ideas for Tunnel-FETs

Design ideas for Tunnel-FETs Samarth Agarwal, Mathieu Luisier and Gerhard Klimeck


  • To explore design ideas for voltage scaling of transistors.


  • VDD scaling : Difficult in MOSFETs, possible in TFETs.
  • gFET: Larger tunneling area gives higher ION than conventional TFETs.
  • Modified and optimized gFET design to meet ITRS requirements.


  • gFET with high ION and low IOFF will provide a viable alternative for VDD scaling to reduce power consumption.

Powerpoint slide as ppt, pdf, or as image below.