Skip navigation

System-on-Chips

AFTx05

 
 
Goal: AFT-X05 will be our second tape-out to MIT-LL on their 90nm FDSOI process. This design incorporates several features intended for research and demonstration including sparsity optimizations of the RISCV core, polymorphic logic, and electromigration test structures. 
 
Status: The design is being prepared for tape-out to take place Dec. 1, 2019. 

 

AFTx04

Goal: AFTx04 is an implementation of a simple microcontroller based on a RISCV core. It is also or first attempt at fabrication through the MIT Lincoln Labs 90nm FDSOI process.
 
Status: The dice passed manufacturing test at MIT-LL and packaged ICs were delivered in September 2019. NSWC Crane engineer is helped the team run functional test vectors on an automated tester. Except for some odd behavior by the debugger on reset, all of the design functions as intended. 
 

AFTx03

 

Goal: AFT-X03’s main focus was to create an SoC with basic functionality. The only supported peripheral is GPIO. This was the team’s first attempt at on-chip SRAM. The simplicity of the chip allows us to focus on establishing a team design flow before moving onto more complex designs

Status: A minimal chip bring up was performed but due to choice in package the chip proved to be very difficult to test mount to a PCB and test.

 

 

AFTx01/AFTx02

Goal: AFT-X01 and AFT-X02 were the team’s first attempt at designing and taping-out an SoC. Both chips have the same architecture. The bus structure of this chip was adopted by all of our current SoCs.

Status: AFT-X01 had an error in the power distribution and could not successfully be powered up. AFT-X02 was successfully powered on during bring-up. We were able to communicate with the debugger through UART.