Research Focus Overview

I.  Brain-Inspired Neuromorphic Computation

  • Algorithms and Architectures:

Neural nets have emerged as one of the most powerful classification tools for cognitive applications. Novel architectures and algorithms in both spiking or non-spiking (Artificial Neural Networks (ANNs)) context for energy-efficient realization of both shallow and deep learning networks are being explored. The new computational theories are directed towards enabling on-chip intelligence for cognitive platforms.

Recent Publications:

          Deep Learning/ANNs:

  1. P. Panda, A. Sengupta, K. Roy, “Conditional Deep Learning for Energy-Efficient and Enhanced Pattern Recognition”, DATE 2016.

  2. P. Panda, A. Ankit, P. Wijesinghe, K. Roy, “FALCON: Feature Driven Selective Classification for Energy-Efficient Image Recognition”, IEEE TCAD 2017.

  3. P. Panda, K. Roy, “Attention Tree: Learning Hierarchies of Visual Features for Large-Scale Image Recognition”, arXiv preprint, arxiv.org/abs/1608.00611.

Spiking Neural Networks:

  1. P. Panda, K. Roy, "Unsupervised Regenerative Learning of Hierarchical Features in Spiking Deep Networks for Object Recognition", IJCNN 2016.

  2. J. Allred, K. Roy, "Unsupervised Incremental STDP Learning using Forced Firing of Dormant or Idle Neurons", IJCNN 2016.

Current Students: Priyadarshini Panda, Jason Allred

Spintronic devices that can offer a direct mapping to neural and synaptic functionalities in artificial and spiking neural networks are being currently explored. Unsupervised/supervised neural computing platforms based on such spintronic devices can potentially lead to ultra-low power and compact pattern recognition systems.

Recent Publications:

  1. G. Srinivasan, A. Sengupta, K. Roy, "Magnetic Tunnel Junction Based Long-Term Short-Term Stochastic Synapse for a Spiking Neural Network with On-Chip STDP Learning", Scientific Reports, 2016.

  2. A. Sengupta, P. Panda, P. Wijesinghe, Y. Kim, K. Roy, "Magnetic Tunnel Junction Mimics Stochastic Cortical Spiking Neurons", Scientific Reports, 2016.

  3. A. Sengupta, M. Parsa, B. Han, K. Roy, "Probabilistic Deep Spiking Neural Systems Enabled by Magnetic Tunnel Junction", IEEE Transactions on Electron Devices, 2016.

          Current Students: Abhronil Sengupta, Gopalakrishnan Srinivasan            
 

II.  Spin-Transfer Torque Devices, Circuits and Systems

Modeling a typical spintronic device requires self consistent solution of magnetization dynamics and electron transport equations. We have developed a simulation framework from the device to circuit level for analyzing spin based novel systems and architectures. The current focus is to model new physical phenomena, for example, use of topological insulators, the spin-Hall effect and electric field assisted switching of spin devices. 

Recent Publications:

  1. A. K. Reza, X. Fong, Z. A. Azim, K. Roy, "Modeling and Evaluation of Topological Insulator/Ferromagnet Heterostructure Based Memory", IEEE TED, 2016. 

  2. X. Fong, Y. Kim, K. Yogendra, D. Fan, A. Sengupta, A. Raghunathan, K. Roy, "Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives", IEEE TCAD (Keynote Paper)

  3. X. Fong, S. Gupta, N. Mojumder, S H. Choday, and K. Roy, "KNACK: A Hybrid Spin-Charge Mixed-Mode Simulator for Evaluating Different Genres of STT-MRAMs", SISPAD 2011.

          Current Students: Akhilesh Jaiswal, Zubair Al Azim, Ahmed Reza, Saima Sharmin            

STT-MRAMs are being projected as the leading emerging memory technology, that can replace silicon based memories in last level cache applications. However, slow write speed, high write energy consumption and various failure mechanisms are the major challenges associated with STT-MRAMs. Low power and reliable memories are being explored using alternative switching mechanisms such as the spin-Hall Effect and the use of architectural solutions like Error Correcting Codes.

Recent Publications:

  1. X. Fong, Y. Kim, R. Venkatesan, S. H. Choday, A. Raghunathan, and K. Roy, “Spin-transfer Torque Memories: Devices, Circuits and Systems”, Proceedings of the IEEE, 2016.

  2. A. Jaiswal, X. Fong, K. Roy "Comprehensive Scaling Analysis of Current Induced Switching in Magnetic Memories Based on In-Plane and Perpendicular Anisotropies", IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2016.

  3. S. Sharmin, A. Jaiswal, K. Roy, "Modeling and Design Space Exploration for Bit-Cells Based on Voltage-Assisted Switching of Magnetic Tunnel Junctions", IEEE TED, 2016.

Current Students: Akhilesh Jaiswal, Saima Sharmin

Spintronic devices have advantages such as non-volatility, miniaturized area and zero leakage. These key advantages have made them alluring for future logic and memory design. All Spin Logic (ASL) is a recently proposed logic style that uses spintronic devices for logic applications. We are exploring an automatic synthesis methodology to design logic circuits using ASL, in addition to new spin-orbit torque-based domino-style spin logic (SOT-DSL).

Recent Publications:

  1. Z. Pajouhi, S. Venkataramani, K. Yogendra, A. Raghunathan, K. Roy, "Exploring Spin-Transfer-Torque Devices for Logic Applications", IEEE TCAD, 2015.

  2. M.-C. Chen, Y. Kim, K. Yogendra, K. Roy, "Domino-Style Spin–Orbit Torque-Based Spin Logic", IEEE Magnetic Letters, 2015.

          Current Students: Mei-Chin Chen 

Non-boolean neuromorphic computing systems where the core neuronal and synaptic functionalities are being emulated by spintronic devices requires a rethinking of circuits and systems for proper interfacing and functioning of the network. This project is focussed on building a device-circuit-system simulation framework for such neural pattern recognition systems.

Recent Publications:

  1. G. Srinivasan, A. Sengupta, K. Roy, "Magnetic Tunnel Junction Enabled All-Spin Stochastic Spiking Neural Network", DATE 2017. (Invited Paper)

  2. A. Sengupta, A,Banerjee, K. Roy, "Hybrid Spintronic-CMOS Spiking Neural Network With On-Chip Learning: Devices, Circuits and Systems", Physical Review Applied, 2016. (Featured in MIT Technology Review: Emerging Technology from arXiV and DoD R&E Science and Technology News Bulletin)

  3. A. Sengupta, K. Roy, "A Vision for All-Spin Neural Networks: A Device to System Perspective", IEEE Transactions on Circuits and Systems-I: Regular Papers, 2016. (ISCAS 2016 Special Issue)

Current Students: Abhronil Sengupta, Gopalakrishnan Srinivasan
 

III.  Spintronic Sensors for Interconnects

Spintronic devices can function as efficient low power sensors for high-speed long-distance interconnect architectures. We are currently exploring the use of Domain-Wall based Spin-Torque sensors at the receiving end of a current-mode interconnect scheme. The use of Magnetic Tunnel Junctions at the detector of an optical interconnect scheme is also being explored.

          Recent Publications:

  1. Z. A. Azim, A. Sharma, K. Roy, "Buffered Spin-Torque Sensors for Minimizing Delay and Energy Consumption in Global Interconnects", IEEE Magnetic Letters, 2016.

  2. Z. A. Azim, A. Sengupta, S. S. Sarwar, K. Roy, "Spin-Torque Sensors for Energy Efficient High-Speed Long Interconnects", IEEE TED, 2016. 

  3. Z. A. Azim, X. Fong, T. Ostler, R. Chantrell, K. Roy, "Laser Induced Magnetization Reversal for Detection in Optical Interconnects", IEEE EDL, 2015.

Current Students: Zubair Al Azim
 

IV.  Approximate Computing

Approximate computing relies on the ability of many systems and applications to self-heal or to tolerate some loss of quality or optimality in the computed result. The main idea is to exploit the inherent error resiliency or error tolerance of the system to achieve energy efficiency, or in other words, trading accuracy with energy consumption. Such trade-off, in most cases, is also associated with performance improvements like faster operations, area reduction etc.

          Recent Publications:

  1. S. S. Sarwar, S. Venkataramani, A. Raghunathan, K. Roy, “Multiplier-less Artificial Neurons Exploiting Error Resiliency for Energy-Efficient Neural Computing”, DATE 2016.

  2. G. Srinivasan, P. Wijesinghe, S. S. Sarwar, A. Jaiswal, K. Roy, “Significance Driven Hybrid 8T-6T SRAM for Energy-Efficient Synaptic Storage in Artificial Neural Networks”, DATE 2016.

  3. P. Wijesinghe, C. M. Liyanagedera and Kaushik Roy, "Fast, Low Power Evaluation of Elementary Functions Using Radial Basis Function Networks", DATE 2017.

Current Students: Syed Shakib Sarwar, Gopalakrishnan Srinivasan, Parami Wijesinghe
 

V.  Oscillator Based Non-Boolean Computation

Spin Torque Nano Oscillators (STNOs) can be efficiently used to perform computations that are unsuitable or inefficient in von-Neumann computing models. Their frequency of oscillation can be in few tens of gigahertz range operating at low input currents. These attractive features and the ability to obtain frequency locking using a variety of techniques, make STNOs an attractive candidate for non-Boolean computation such as edge detection of an image, associative computing, pattern recognition, etc.

          Recent Publications:

  1. K. Yogendra, D. Fan, K. Roy, "Magnetic Pattern Recognition using Injection Locked Spin Torque Nano-Oscillators", IEEE TED 2016.

  2. C. M. Liyanagedera, K. Yogendra,  D. Fan, K. Roy, " Spin torque nano-oscillator based Oscillatory Neural Network", IJCNN 2016. (Best student paper nomination)

  3. K. Yogendra, D. Fan, K. Roy, "Coupled Spin Torque Nano Oscillators for Low Power Neural Computation", IEEE TMAG, 2015.

Current Students: Yong Shim, Chamika Liyanagedera, Minsuk Koo
 

VI.  Transistors in Sub-10nm Technologies

Sub-10nm technology is expected to have severe short channel effects along with new leakage mechanisms such as direct source-to-drain tunneling. In order to improve the leakage and to obtain highest performance in these deeply-scaled device circuits, we are investigating various types of transistors such as FinFETs, Schottky barrier FETs, and tunneling field-effect-transistors (TFET). We are exploring the design space of such transistors to optimize for sub-10nm technology, and analyze their behaviors in circuits.

          Recent Publications:

  1. A. Sharma, A. K. Reza, K. Roy, “Proposal of an Intrinsic-Source Broken-Gap Tunnel-FET to Reduce Band-Tail Effects on Subthreshold-Swing: A Simulation Study”, IEEE TED, 2016.

  2. A. Sharma, A. ArunGoud, J. P. Kulkarni, K. Roy, “Source-underlapped GaSb-InAs TFETs with applications to Gain Cell Embedded DRAMs”, IEEE TED, 2016.

  3. W.-S. Cho, K. Roy, "The effects of direct source-to-drain tunneling and variation in the body thickness on (100) and (011) sub-10nm Si double-gate transistors," IEEE EDL, 2015.

Current Students: Ankit Sharma
 
 

 
 
 
 
 
 

Past Research Areas

 
 
 

I. Ultralow Voltage Subthreshold Circuits and systems
 
Brief Info: For ultralow power and portable applications, design of digital subthreshold logic is investigated with transistors operated in the subthreshold region (supply voltage corresponding to Logic 1, less than the threshold voltage of the transistor). The subthreshold leakage current of the device is used for computation. Standard design techniques suitable for superthreshold design can be used in the subthreshold region. However, it has been shown that a complete co-design at all levels of hierarchy (device, circuit, and architecture) is necessary to reduce the overall power consumption while achieving acceptable performance (hundreds of kilohertz) in the subthreshold regime of operation.

The chief areas of research in this field include:

1.Device modeling and optimization for subthreshold operation (both in bulk and SOI technologies)

2.Choice of circuit and architecture suitable for subthreshold operation

3.Analysis of PVT variations in subthreshold designs

4.Subthreshold memory design



Current Students: Ik-Joon Chang, Jaydeep Kulkarni
Recently Graduated Students: Arijit Raychowdhury, Myeong-Eun Hwang, Hendrawan Soeleman, Animesh Datta, Pooja Batra
 

 

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II. Designing circuits beyond traditional Silicon
 
Brief Info: Scaling of Silicon technology continues while research has started in other novel materials for future technology generations beyond the year 2015. Carbon nanotubes (CNTs) with their excellent carrier mobility are a promising candidate. We investigated different carbon nanotube based field effect transistors (CNFETs) for an optimal switch. Schottky Barrier (SB) CNFETs, MOS CNFETs, and state-of-the-art Si MOSFETs were systematically compared from a circuit/system design perspective. We are working on developing compact models for carbon nanotube based transistors, interconnects with metallic nanotubes as well as developing tools and software to evaluate circuit/system level performance of nanotube based digital circuits. We are also working on other technological options beyond traditional silicon. These include nanowires, III-V high mobility transistors, computation with nano magnets, Spin FETs, as well as two terminal molecular devices.

The chief areas of research in this field include:

1.Carbon Nano Tube based circuits(both BTBT CNT and CNTFET)

2.Polysilicon TFT based on Carbon Nano Tubes

3.Magnetic Quantum Cellular Automata(MQCA) based circuits and architectures

4.Subthreshold memory design



Current Students: Charles Augustine, Sumeet Gupta, Niladri Mojumder, Xuanyao Fong, Kerem Camsari, Jaydeep Kulkarni Jing Li
Recently Graduated Students: Arijit Raychowdhury, Qiaki Chen
 

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III. Signal Processing Architectures using Magnetic QCA(MQCA)
 
Brief Info: Tremendous amount research effort has been put into scale the MOSFET to the ultimate limits of molecular dimension. And at the same time several other devices has been investigated to work as replacement for silicon. Magenetic Quantum Cellular Automata is one among the promising candidates. We are working on developing compact models for MQCA as well as developing software to evaluate circuit/system level performance of Signal Processing circuits using MQCA.

Current Students: Charles Augustine, Xuanyao Fong, Sumeet Gupta
Recently Graduated Students: Arijit Raychowdhury
 

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IV. High Performance and Low Power Flexible Electronics
 
Brief Info: Low Temperature Polycrystalline Silicon Thin Film Transistors (LTPS TFTs) have been widely used in Active Matrix Liquid Crystal Display (AMLCD) as pixel-switching-elements with high supply voltage (10~20V). These devices are low performance (due to thick silicon body and gate oxide) and hence, not suitable for both high performance and low power digital circuits. In keeping with the general trend of the CMOS technology, LTPS TFTs can also be scaled to sub-micron regime. The scaled device can achieve higher performance than standard TFTs and can be a promising candidate for both sub-threshold and super-threshold operation.

The chief areas of research in this field can be summarized below:

1.Device modeling and optimization for super- and sub-threshold operation (extent to organic TFTs)

2.Modeling and Analysis of inherent process variation (GBs induced variation) in scaled TFT technology

3.Statistical timing analysis and variation tolerant design in circuit/architecture considering the inherent variations to improve yield



Current Students: Jing Li, Himanshu Markendeya, Selin Baytok
Recently Graduated Students: Swaroop Ghosh, Aditya Bansal
 

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V. Green Computing(Ultra Low Power Electronics)
 


Current Students: Jaydeep Kulkarni, Charles Augustine, Xuanayo Fong,
Recently Graduated Students: Arijit Raychowdhury, Nilanjan Banerjee, Amit Agarwal, Yiran Chen, Animesh Datta, Swarup Bhunia, H. Mahmoodi
 

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VI. Low Power, Variation Aware System design
 
Brief Info: The two major issues being faced by today's IC designers are power and process variation. Concurrently addressing both these issues is a challenging task since low power schemes and process tolerant methods represent contradictory requirements in terms of system design. To target these issues simultaneously, novel design methodologies are required. We observed that for a certain class of systems (especially digital signal processing systems) by allowing the "right tradeoffs" between output quality and power requirements, voltage scaling for low power dissipation can be obtained even in presence of process parameter variations. We investigate and develop novel designs for such systems in this research.

Current Students: Georgios Karakonstantis, Charles Augustine, Debabrata Mohapatra, Jung-Hwan Choi, Xuanyao Fong, Patrick Ndai
Recently Graduated Students: Nilanjan Banerjee
 

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VII. Memory Technology and Design
 
Brief Info: Embedded cache memories are expected to occupy 90% of the total die area of a system-on-a-chip. Nano-scaled SRAM bitcells having minimum sized transistors are vulnerable to inter-die as well as intra-die process variations. Intra-die process variations include random dopant fluctuation (RDF), line edge roughness (LER) etc. We are developing device, circuit and architecture level techniques for robust, low power nano-scaled memory technologies.

The chief areas of research in this field can be summarized below:

1.Process variation tolerant design of nano scaled SRAM bitcell and peripheral design

2.Process variation aware design of STT MRAM bitcell/architecture (STT-Spin Transfer Torque)

Current Students: Jaydeep Kulkarni, Ashish Goel, Ik-joon Chang, Jing Li
Recently Graduated Students: S. Mukhopadhyay, Chris Kim, Hamid Mahmoodi, Amit Agarwal, Aditya Bansal, Saakshi Gangwal, Dheepa Lekshmanan
 

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VIII. Process Variations and Error Resilience
 


Current Students: Patrick Ndai, Ashish Goel
Recently Graduated Students: Kunhyuk Kang, Swaroop Ghosh, Nilanjan Banerjee, Myeong-Eun Hwang, Keejong Kim, Keejong Kim, Ali. Keshavarzi, Naran. Sirisantana, Seung-Hoon Choi, Yonghee Im, Woopyu Jeong, Shiyou Zhao, Dinesh Somashekhar, Cassandra Crotty Neau, Chris Hyungil Kim, Swarup Bhunia, Bipul Paul, Hamid Mahmoodi, Saibal Mukhopadhyay, Amit Agarwal, Yiran Chen, Animesh Datta, James D. Gallagher
 

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IX. Reliability
 
Brief Info: Achieving a satisfactory level of lifetime reliability has become a challenging task in scaled technologies due to the increased reliability issues such as Negative Bias Temperature Instability (NBTI), Time Dependent Dielectric Breakdown (TDDB), Hot Carrier Injection (HCI), electro-migration, etc. In this lab, we are working on modeling and analysis of some of the most alarming reliability concerns, such as NBTI. In addition, we are developing elegant techniques to alleviate the reliability problems at both circuit and design synthesis level.

Current Students: Sang Phill Park, George Panagopoulos, Niladri Mojumder
Recently Graduated Students: Kunhyuk. Kang, Keejong Kim, Saakshi Gangwal
 

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X. Scaled CMOS Devices/Circuits (Double-Gate Technology)
 


Current Students: Ashish Goel, Jaydeep Kulkarni, Niladri Mojumder
Recently Graduated Students: Deepha Lekshmanan, Qikai Chen, Saakshi Gangwal, Tamer Cakici, Amit Agarwal, Cassondra Neau, Chris Kim, Hamid Mahmoodi, Hari Ananthanarayanan, Jae-Joon Kim, Liqiong Wei, Rongtian Zhang, Saibal Mukhopadhyay
 

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XI. VLSI Test and Fault Tolerance
 
Brief Info: Sub-wavelength lithography has led to large variation in transistor geometries and flat-band voltage while intrinsic variations in nano-scaled devices such as line-edge roughness (LER), random dopant fluctuations (RDF), or body thickness variations in thin body SOI have led to large spatial variations in transistor threshold voltage. Such variations along with higher levels of integration can lead to large spread in circuit delay, power, and robustness across different dies. Parameter variations adversely affect minimum geometry circuits such as SRAM cells leading to read, write, access time, and hold failures, while logic circuits may experience parametric failures such as delay, or excessive leakage. To reduce test cost and improve yield, design and test should be considered together. We propose an integrated on-chip tester/BIST and design-for-test circuitries to reduce test cost; sensors to detect process corners; and design and post-Silicon techniques to avoid/repair failures to improve yield.

The overall design and test approach is as follows:.

1. Modeling of process variation and failures

2. Design-for-testability

3. On-chip tester/BIST

4. Post-silicon self-calibration and self-repair for improved yield

5. Pre-silicon self-repairing for logic.



Current Students: Ashish Goel, Jing Li, Mesut Meterelliyoz
Recently Graduated Students: Swaroop Ghosh, Arijit Raychowdhury, Qikai Chen, Swarup Bhunia, Saibal Mukhopadhyay, Naran Sirisantana, Ali Keshavarzi, Zhanping Chen, Xiaodong Zhang, Khurram Muhammad
 

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