Descritpion: Using PETE one can evaluate any MOSFET like devices or any New Devices in terms of performance on Benchmark circuits. The input to the tool can be in terms of typical MOSFET parameters or in terms of I-V and C-V tables. The Benchmark circuits include minimum sized inverter, nand chain, norchain, 8-bit Full Adder, Ring Oscillator and Cascaded inverters driving a big load capacitance. Further, one can perform DC simulations on inverters and obtain voltage transfer characteristics (VTCs) and noise margin/ gain from the VTC.

Purdue Exploratory Technology Evaluator

Tutorial on PETE

Compiled_Publications

Compiled_Publications

Compiled_Publications

Selected_Publications

Journal Papers

2007

1. A. Raychowdhury and K. Roy, "Carbon Nanotube Electronics: Design of High Performance and Low Power Digital Circuits," IEEE Transactions on Circuits and Systems -- I, special issue on Nanotechnology, to appear

2006

1. A. Raychowdhury, A. Keshavarzi, J. Kurtin, V. De, and K. Roy, Analysis of Carbon Nanotube Field Effect Transistors for High Performance Digital Logic - Modeling and DC Simulations, IEEE Transactions on Electron Devices, Vol. 53, Issue 11, November 2006, pp: 2711-2717.

2. A. Keshavarzi, A. Raychowdhury, J. Kurtin, K. Roy, and V. De, Analysis of Carbon Nanotube Field Effect Transistors for High Performance Digital Logic Transient Analysis, Parasitics and Scalability, IEEE Transactions on Electron Devices, Vol. 53, Issue 11, November 2006, pp: 2718-2726.

3. A. Raychowdhury and K. Roy, Modeling of Metallic Carbon Nanotube Interconnects for Circuit Simulations and a Comparison with Cu Interconnects for Scaled Technologies, IEEE Transactions on Computer Aided Design, Vol. 25, Issue 1, January 2006, pp: 58-65.

4. A. Raychowdhury and K. Roy, Carbon nanotube based voltage-mode multiple-valued logic design, IEEE Transactions on Nanotechnology, Vol. 4, Issue 2, March 2005, pp: 168 - 179.

2005

5. M. Hwang, A. Raychowdhury, and K. Roy, Energy Recovery Techniques to Reduce On-chip Power Density in Molecular Nano-Technologies, IEEE Transactions on Circuits and Systems I, Vol. 52, no. 8, August 2005, pp: 1580-1589.

2004

6. A. Raychowdhury, S. Mukhopadhyay and K. Roy, A Circuit Compatible Model of Ballistic Carbon Nanotube Field Effect Transistors, IEEE Transactions on Computer Aided Design, Vol. 23, no. 10, October 2004, pp: 1411-1420.

Conference Papers

2006:

1. A. Raychowdhury, X. Fong, Q. Chen, and K. Roy, Analysis of Super Cut-off Transistors for Ultralow Power Digital Logic Circuits, Proc. of the International Symposium of Low Power Electronic Design (ISLPED), October 2006, pp: 1-6. (Best paper Award)

2. M. Budnik, A. Raychowdhury, Aditya Bansal and K. Roy, CNCAP: Design of a high density Carbon Nanotube Capacitor Structure, Proc. of the Design Automation Conference (DAC), July 2006.

3. A. Raychowdhury, J. Kim, D. Peroulis, and K. Roy, Integrated MEMS Switches for Leakage Control of Battery Operated Systems, Proc. of the Custom Integrated Circuit Conference (CICC), September 2006.

4. A. Raychowdhury, and K. Roy, Using Super Cut-off Carbon Nanotube Sleep Transistors in Silicon Based Low Power Digital Circuits, Proc. of the IEEE Nano, Cincinnati, September 2006.

5. A. Raychowdhury, A. Keshavarzi, J. Kurtin, V. De, and K. Roy, Optimal Spacing of Carbon Nanotubes in a CNFET Array for Highest Circuit Performance, Proc. of the Device Research Conference (DRC), June 2006.

6. A. Raychowdhury, and K. Roy, Carbon Nanotubes for Digital Circuit Design, Proc. of the Government Microcircuit Applications and Critical Technology Conference, GomacTech, March 2005. (Invited)

7. M. Budnik, A. Raychowdhury, K. Roy, Power Delivery for Nanoscale Processors with Single Wall Carbon Nanotube Interconnects, Proc. of the IEEE Nano, Cincinnati, September 2006.

2005

8. A. Raychowdhury, Jing Guo, K. Roy, and Mark Lundstrom, Design of a novel three-valued static memory using Schottky barrier carbon nanotube FETs, Proc. of the Fourth IEEE Nano Conference, Munich, July 2005, pp: 507 510.

2004

9. A. Raychowdhury and K. Roy, Carbon Nanotubes as Interconnects of the Future: A Circuit Perspective, Proc. of the Advanced Metallization Conference, San Diego, October 2004. (Invited)

10. A. Raychowdhury and K. Roy, Circuit Modeling of Carbon Nanotube Interconnects and their Performance Estimation in VLSI Design, Proc. of the International Workshop on Computational Electronics (IWCE), West Lafayette, October 2004.

11. A. Raychowdhury and K. Roy, A Circuit Model for Carbon Nanotube Interconnects: Comparative Study with Cu Interconnects for Scaled Technologies, Proc. of the International Conference on Computer Aided Design (ICCAD), San Jose, November 2004, pp: 237-240.

12. A. Raychowdhury and K. Roy, Modeling and Analysis of Carbon Nanotube Interconnects for High Speed VLSI Design, Proc. of the Fourth IEEE Nano Conference, Munich, August 2004, WE-P-37.

13. A. Raychowdhury, Jing Guo, K. Roy, and Mark Lundstrom, Choice of Flat-Band Voltage, VDD and Diameter of Ambipolar Schottky-Barrier Carbon Nanotube Transistors in Digital Circuit Design, Proc. of the Fourth IEEE Nano Conference, Munich, August 2004, TH-2-2-1.

14. A. Raychowdhury and K. Roy, A Novel Multiple-Valued Logic Design Using Ballistic Carbon nanotube FETs, Proc. of the 34th International Symposium on Multiple-Valued Logic (ISMVL), Toronto, May 2004, pp: 14-19.

2003

15. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation, Proc. of the International Conference on Computer Aided Design (ICCAD), San Jose, November 2003, pp: 465-469.

16. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, Circuit-compatible modeling of carbon nanotube FETs in the ballistic limit of performance, Proc. of the Third IEEE-Nano Conference, San Francisco, August 2003, pp: 343-346. (Best Paper Award)

17. A. Raychowdhury and K. Roy, Performance Estimation in Molecular Crossbar Architecture Considering Capacitive and Inductive Coupling Between Interconnects", Proc. of the Third IEEE-Nano Conference, San Francisco, August 2003, pp: 445-448.

Selected_Publications

Journal Publications:

2007

1. Jing Li, A. Bansal and K. Roy; Poly-Si Thin Film Transistors: An efficient and low cost option for digital sub-threshold operation, accepted for publication in IEEE Transactions on Electron Devices (TED), 2007.

Conference Publications:

2007

1. Jing Li, K. Kang, A. Bansal and K. Roy, High performance and low power electronics on flexible substrates, accept by Design Automation Conference (DAC), 2007.

2. Jing Li, K. Kang and K. Roy, Novel variation-aware circuit design of scaled LTPS TFT for ultra low power, low-cost applications, accept by Intl. Conf. on IC Design & Technology (ICICDT), 2007

2006

1. Jing Li, A. Bansal and K. Roy; Exploring low temperature Poly-Si for low cost and low power sub-micron digital operation, Device Research Conference (DRC), 2006.

Selected_Publications

Journal Publications:

2007

1. N. Banerjee, A Raychowdhury, K. Roy, S. Bhunia, and H. Mahmoodi, Low Power Datapath Synthesis Using Supply Gating Based Operand Isolation Techniques, IEEE Transactions on VLSI Systems (TVLSI), to appear

2006

4. N. Banerjee, A Raychowdhury, K. Roy, S. Bhunia, and H. Mahmoodi, Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis, IEEE Transactions on VLSI Systems, September 2006, pp. 1034-1039. (no 118)

2005

4. S. Bhunia, A. Datta, N. Banerjee, and K. Roy, GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks, IEEE Transactions on Computer, special issue on low-power design, June 2005, pp. 752-766. (no. 99)

2002

2. A. Solomatnikov, D. Somasekhar, N. Sirisantana, and K. Roy, Skewed CMOS: Noise Tolerant High Performance and Low Power Static Circuit Family, IEEE Transactions on VLSI Systems, pp. 469-476, August 2002.

Conference Publications

2006

10. N. Banerjee, H. Mahmoodi, S. Bhunia, and K. Roy, Low Power Synthesis of Dynamic Logic Circuits using Fine-Grained Clock Gating, IEEE Design and Test in Europe (DATE), March 2006. (no 411)

2005

12. N. Banerjee, A. Raychowdhury, S. Bhunia, H. Mahmoodi, and K. Roy, Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis, IEEE International Conference on Computer Design (ICCD), October 2005.(no 396)

13. S. Bhunia, H. Mahmoodi, N. Banerjee, Q. Chen, and K. Roy, A Novel Synthesis Approach for Active Leakage Power Reduction Using Supply Gating, IEEE/ACM Design Automation Conference (DAC), June 2005.(no 384)

14. A. Datta, S. Bhunia, S. Mukhopadhyay, and K. Roy, Statistical Modeling of Pipeline Delay and Design of Pipeline Under Process Variation to Enhance Yield in Sub-100nm Technologies, IEEE Design and Test in Europe (DATE), pp. 926-931, 2005. (no 373)

15. A. Datta, S. Bhunia, N. Banerjee, and K. Roy, A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks, IEEE International Symposium on Quality Electronic Design, pp.358-363, 2005. (no 365)

2003

10. Y. Chen, K. Roy, and C-K. Koh, Integrated Architectural/Physical Planning Approach for Minimization of Current Surge in High Performance Clock-Gated Microprocessor, IEEE International Symposium on Low-Power Electronics and Design, pp. 229-234, August 2003. (no 316)

11. A. Agarwal and K. Roy, A Noise Tolerant Cache Design to Reduce Gate and Subthreshold Leakage in the Nanometer Regime, IEEE International Symposium on Low-Power Electronics and Design, pp. 18-21, August 2003. (no 314)

12. W. Jeong and K. Roy, Robust High-Performance Low-Power Carry Select Adder, IEEE AsiaSouth-Pacific Design Automation Conference, January 2003. (no 204)

2001

5. J. Kim and K. Roy, A Leakage Tolerant High Fan-in Dynamic Circuit Design Technique, European Solid State Circuits Conference, September 2001.(no 267)

6. N. Sirisantana, A. Caoa, S. Davidson, C. Koh, and K. Roy, Selectively Clocked Skewed Logic (SCSL): A Robust Low-Power Logic Style for High-Performance Applications, ACM/IEEE International Symposium on Low Power Electronics and Design, August 2001, pp. 267-270. (no 265)

Selected Journal Publications:

2008

1) J.H. Choi, N. Banerjee, and Kaushik Roy, Variation-Aware Low-Power Synthesis Methodology for Fixed-Point FIR Filters,IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems(to appear)

Selected Conference Publications:

2007

1) Process Variation Tolerant Low Power DCT Architecture, IEEE Design, Automation and Test in Europe (DATE), April 2007

2) An Optimal Algorithm for Low Power Multiplierless FIR Filter Design Using Chebychev Criterion, ICASSP 2007

Selected_Publications

Journal Publications:

2007

1. S. Mukhopadhyay, K. Kim, K. Kang, H. Mahmoodi-Meimand, A. Datta, Dongkyu Park and K. Roy, "Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS," accepted for publication in IEEE Journal of Solid State Circuits

2. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, Reduction of Parametric Failures in Sub-100nm SRAM Array using Body Bias, accepted for publication in IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems

3. A. Bansal, S. Mukhopadhyay, and K. Roy, Device Optimization Technique for Robust and Low-Power FinFET SRAMs, accepted for publication in IEEE Transactions on Electron Devices.

2006

1. C. H. Kim, J. Kim, I. Chang, and K. Roy, "PVT Aware Leakage Reduction for On-Die Caches Using Self-Decay Scheme", IEEE Journal of Solid-State Circuits, Vol. 41, Issue 1, pp. 170-178, Jan. 2006

2. S. Mukhopadhyay, Hamid Mahmoodi, and K. Roy, Design of High Performance Sense Amplifier Using Independent Gate Control in Fully Depleted Double-Gate MOSFET, IEEE Transaction on VLSI Systems (TVLSI), March, 2006.

2005

1. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in Nano-Scaled CMOS, IEEE Transaction on Computer Aided Design of Integrated Circuits and Systems , Dec. 2005.

2. A. Agrawal, B. Paul, H. Mahmoodi, A. Datta, and K. Roy, "A Process-Tolerant Cache Architecture for Improved Yield in Nanoscale Technologies," IEEE Transactions on Very Large Scale Integration Systems, vol. 13, no. 1, pp. 27-38, Jan. 2005

3. A. Agarwal, B. Paul, S. Mukhopadhyay, and K. Roy, Process Variation in Embedded Memories: Failure Analysis and Process Tolerant Architecture, IEEE Journal of Solid State Circuits , Sept. 2005

4. C. Kim, J. Kim, S. Mukhopadhyay, and K. Roy, A Forward Body-Biased Low-Leakage SRAM Cache: Device and Architecture Considerations, IEEE Transactions on VLSI Systems, March 2005.

Conference Publications:

2008

1. N. N. Mojumder, S. Mukhopadhyay, J. Kim, C. T. Chuang, K. Roy, "Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry," IEEE VLSI Test Symposium 2008, April 2008

2007

1. J. P. Kulkarni and K. Roy A High Performance Scalable Multiplexed Keeper Technique 2007 International Symposium on Quality Electronics Design (ISQED), pp. 545-549, March 2007

2006

1. S. Gangwal, S. Mukhopadhyay and K. Roy, Optimization of Surface-orientation for high performance, low power and robust FinFET SRAM, CICC 2006.

2. A. Goel, S. Bhunia, H. Mahmoodi and K. Roy, Low-Overhead Design of Soft-Error-Tolerant Scan Flip-Flops with Enhanced-Scan Capability, Asia South Pacific Design Automation Conference 2006.

3. S. Mukhopadhyay, K. Kim, H. Mahmoodi, A. Datta, D. Park, and K. Roy, Self-Repairing SRAM for Reducing Parametric Failures in Nanoscaled Memory, Symp. on VLSI Circuits, 2006.

4. S. Mukhopadhyay, A. Agarwal, Q. Chen, and K. Roy, SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design (INVITED), IEEE Custom Integrated Circuit Conference, 2006.

5. S. Mukhopadhyay, S. Ghosh, K. Kim, and K. Roy, Low-Power and Process Variation Tolerant Memories in sub-90nm Technologies (INVITED), IEEE Intl. System-On-Chip Conf., 2006.

2005

1. A. Bansal, S. Mukhopadhyay and K. Roy, Modeling and Optimization Approach to Robust and Low-Power FinFET SRAM Design in Nanoscale Era. Proc. of the IEEE Custom Integrated Circuits Conference (CICC), 2005, pp. 835-838.

2. I. J. Chang, K. Kang, S. Mukhopadhyay, C.H. Kim, K. Roy, Fast and Accurate Estimation of Nano-Scaled SRAM Read Failure Probability using Critical Point Sampling, Custom Intergrated Circuit Conference (CICC), Sep. 2005

3. C. H. Kim, J. Kim, I. Chang and K. Roy, "PVT-Aware Leakage Reduction for On-die Caches with Improved Read Stability", International Solid-State Circuits Conference (ISSCC), Feb. 2005

4. K. Kim, C. H. Kim, and K. Roy, "TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique", International Symposium on Quality Electronics Design (ISQED), Mar. 2005

5. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Design of High Performance Sense Amplifier Using Independent Gate Control in Fully Depleted Double-Gate MOSFET," Intl. Symp. on Quality Electronic Design (ISQED), 2005.

6. S. Mukhopadhyay, K. Kang, H. Mahmoodi, and K. Roy, Reliable and Self-Repairing SRAM in Nano-scale Technologies using Leakage and Delay Monitoring, Intl. Test Conf. (ITC), 2005.

7. S. Mukhopadhyay, A. Raychowdhury, H. Mahmoodi, and K. Roy, Leakage current based stabilization scheme for robust sense-amplifier design for yield enhancement in nano-scale SRAM, Asian Test Symp. (ATS), 2005.

2004

1. H. Ananthan, A. Bansal and K. Roy, FinFET SRAM - Device and Circuit Design Considerations. Proceedings of the International Symposium on Quality Electronic Design (ISQED), 2004, pp. 511-516.

2. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Modeling and Estimation of Failure Probability due to Parameter Variations in Nano-scale SRAMs for Yield Enhancement," Symp. on VLSI Circuits, 2004.

3. S. Mukhopadhyay, H. Mahmoodi, and K. Roy, "Statistical Design and Optimization of SRAM Cell for Yield Enhancement," Intl. Conf. on Computer Aided Design, 2004.

2003

1. C. H. Kim, J. Kim, S. Mukhopadhyay, and K. Roy, "A Forward Body-Biased Low-Leakage SRAM: Device and Architecture Considerations", International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2003

2002

1. C. H. Kim, K. Roy, "Dynamic Vth SRAM : A Leakage Tolerant Cache Memory for Low Voltage Microprocessors ", International Symposium on Low Power Electronics and Design (ISLPED), Aug. 2002

2. H. Mahmoodi and K. Roy, Self-precharging flip-flop (SPFF): a new level converting flip-flop, European Solid-State Circuits Conference, pp. 407-410, Sep. 2002

Selected_Publications

Journal Publications:

2008

1. A. Datta, S. Bhunia, J.H. Choi, S. Mukhopadhyay, and K. Roy, Profit Aware Circuit Design under Process Variations Considering Speed Binning IEEE TVLSI, July 2008

2007

1. S. Ghosh, S. Bhunia, and K. Roy, CRISTA: A New Paradigm for Low-power, Variation-Tolerant and Adaptive Circuit Synthesis Using Critical Path Isolation, IEEE Transactions on Computer-Aided Design of ICs, to appear. (no. 134)

2. Kunhyuk Kang, Haldun Kufluoglu, Kaushik Roy, and Muhammad A. Alam, "Impact of Negative Bias Temperature Instability in Nano-Scale SRAM Array: Modeling and Analysis," IEEE Transactions on Computer Aided Design of ICs, to appear.

3. Amit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher and Kaushik Roy, "Device-Aware Yield-Centric Dual-Vt Design under Parametric Variations in Nano-Scale Technologies," IEEE Transactions on VLSI, to appear

4. Saibal Mukhopadhyay, Keejong Kim, Kunhyuk Kang, Hamid Mahmoodi, Animesh Datta, Dongkyu Park and Kaushik Roy, "Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS," accepted for publication in IEEE Journal of Solid State Circuits.

5. B. Paul, K. Kang, H. Kufluoglu, M. Alam, and K. Roy, ``Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits, April 2007, pp. 743-751. (no 125)

2006

1. A.Datta, S. Bhunia, S. Mukhopadhyay, and K. Roy, ``Modeling of Pipeline Delay and Statistical Design of Pipeline under Process Variations,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits}, November 2006, pp. 2427-2436. (no 123)

2. K. Kang, B. Paul, and K. Roy, Statistical Timing Analysis using Levelized Covariance Propagation Considering Systematic and Random Variations of Process Parameters, ACM Transactions on Design Automation of Electronic Systems, vol. 11, no. 4, October 2006, pp. 848-879. (no 122)

3. C.H. Kim, K. Roy, S. Hsu, R. Krishnamurthy, and S. Borkar, A Process variation Compensating Technique With an On-Die Leakage Current Sensor for Nanometer Scale Dynamic Circuits, IEEE Journal of Solid-State Circuits, June 2006, pp. 646-649. (no 115)

2005

1. H. Mahmoodi, S. Mukhopadhyay, and K. Roy, Estimation of Delay Variations due To Random-Dopant Fluctuations in Nanoscale CMOS Circuits, IEEE Journal of Solid-State Circuits, September 2005, pp. 1787-1796. (no 103)

2. B. Paul, K. Kang, H. Kufluoglu, A. Alam, and K. Roy, Impact of NBTI on the Temporal Performance Degradation of Digital Circuits, IEEE Electron Device Letters, August 2005, pp. 560-562. (no 101)

3. A. Agarwal, B. Paul, H. Mohammadi, A. Datta, and K. Roy, A Process Tolerant Cache Architecture for Improved Yield in Nanoscale Technologies, IEEE Transactions on VLSI Systems, January 2005, pp. 27-38. 2005 IEEE Circuits and Systems Society VLSI Transactions Best Paper Award. (no. 85)

2002

1. A. Keshavarzi, K. Roy, J. Tschantz, S. Narendra, A. Daasch, C. Hawkins, and V. De, Impact of Leakage and Process Variation on Current-Based Testing for Future Scaled CMOS Circuits, IEEE Design and Test, September-October 2002, pp. 36-43. (no 66)

Conference Publications:

2007

1. S. Ghosh, S. Bhunia, and K. Roy,A Fault Tolerant Technique for Improved Yield in Nanometer Technologies by Adaptive Clock Stretching, International On-Line Test Symposium, 2007. (no 444)

2. M. Hwang, K. Kim, A. Raychowdhury, and K. Roy, An 85mV 40nW Process Tolerant Subthreshold 8x8 FIR Filter in 130nm Technology, IEEE VLSI Circuit Symposium, June 2007. (no 442)

3. Kunhyuk Kang, Keejong Kim, and Kaushik Roy, "Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop," accepted for publication in Design Automation Conference, June 2007. (no 439)

4. Kunhyuk Kang, Keejong Kim, Ahmad E. Islam, Muhammad A. Alam, and Kaushik Roy, "Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement," accepted for publication in Design Automation Conference, June 2007, nominated for best-paper award.

5. Kunhyuk Kang, Muhammad A. Alam, and Kaushik Roy, "Estimation of NBTI Degradation Using On-Chip IDDQ Measurement," IEEE International Reliability Physics Symposium, April 2007, pp. 10-16.

6. M. Hwang, T. Cakici, A. Raychowdhury, and K. Roy, Process Variation Tolerant Beta-ratio Modulation with Ultra Dynamic Voltage Scaling, Design Automation and Test in Europe, April 2007, nominated for best-paper award. (no 436)

7. N. Banerjee, G. Karakonstantis, and K. Roy, Process Variation Tolerant Low-Power DCT Architecture, Design Automation and Test in Europe, April 2007. (no 435)

8. S. Ghosh, S. Bhunia, and K. Roy, Low-Overhead Circuit Synthesis for Temperature Adaptation using Dynamic Voltage Scheduling, Design Automation and Test in Europe, April 2007. (no 434)

9. S. Mukhopadhyay, K. Kim, K. Jenkins, C.-T. Chuang, and K. Roy,Statistical Characterization and On-Chip Measurement Methods for Local Random Variability Using Sense-Amplifier-Based Test Structure, 2007 International Solid-State Circuits Conference (ISSCC), February 2007., pp 400-402 (no 431)

2006

1. S. Ghosh, S. Bhunia, and K. Roy, A New Paradigm for Low-power, Variation-Tolerant and Adaptive Circuit Synthesis Using Critical Path Isolation, IEEE International Conference on Computer-Aided Design of ICs , 2006. (no 429)

2. Kunhyuk Kang, Haldun Kufluoglu, Muhammad A. Alam, and Kaushik Roy, "Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI," IEEE International Conference on Computer Design, October 2006, pp. 216-221.

3. S. Mukhopadhyay, A. Agarwal, Q. Chen and K. Roy, SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design, IEEE Custom Integrated Circuits Conference, September 2006, Invited Paper. (no 426)

4. S. Mukhopadhyay, K. Kim, H. Mahmoodi, A. Datta, D. Park, and K. Roy, Self-Repairing SRAM for Reducing Parametric Failures in NanoscaledMemory, IEEE 2006 Symposium on VLSI Circuits, June 2006. (no 416)

5. B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam and K. Roy,Temporal Performance Degradation Under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits, IEEE Design and Test in Europe (DATE), March 2006.

6. Kunhyuk Kang, Muhammad A. Alam, and Kaushik Roy, "Analysis and Design of Nano-Scale Digital CMOS Circuits under Spatial and Temporal Reliability Degradation," SRC Student Symposium, 2006.

7. A. Goel, S. Bhunia, H. Mahmoodi, and K. Roy, A Low-Overhead Design of Soft-Error-Tolerant Scan Flip-Flop with Enhanced-Scan Capability, Asia and South Pacific Design Automation Conference, pp. 665-670, January 2006. (no 407)

8. H. Li, Y. Chen, K. Roy, and C.-K. Koh, SAVS: A Self-Adaptive Variable Supply Voltage Technique for Process-Tolerant and Power-Efficient Multi-Issue Superscalar Processor Design, Asia and South Pacific Design Automation Conference, pp. 158-163, January 2006 (no. 406)

9. A. Datta, S. Bhunia, S Mukhopadhyay, J. Choi, and K. Roy, Speed Binning Aware Design Methodology to Improve Profit under Parameter Variation, Asia and South Pacific Design Automation Conference, January 2006, pp. 712 717, nominated for best paper award (no 405)

2005

1. A. Datta, S. Bhunia, S. Mukhopadhyay, and K. Roy, A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations, 14th Asian Test Symposium, December 2005. (no 401)

2. A. Agarwal, K. Kang, and K. Roy, Accurate Estimation and Modeling of Total Chip Leakage Considering Inter- and Intra-Die Process Variations, IEEE International Conference on ComputerAided Design (ICCAD), November 2005. (no 400)

3. P. Ndai, A. Agarwal, Q. Chen, and K. Roy, A Soft-Error Monitor Using Switching Current Detection, IEEE International Conference on Computer Design (ICCD), October 2005. (no 394)

4. Y. Chen, H. Li, K. Roy, and C.-K. Koh, Cascaded Carry-Select Adder (C2SA): A New Structure for Low-Power CSA Design, ACM/IEEE International Symposium on Low-Power Electronics and Design, August 2005, pp. 115-118. (no 388)

5. S. Hsu, A. Agarwal, K. Roy, R. Krishnamurthy, and S. Borkar, An 8.3 GHz Dual Supply/Threshold Optimized 32b Integer ALU-Register File Loop in 90nm CMOS, ACM/IEEE International Symposium on Low-Power Electronics and Design, August 2005, pp. 103-106. (no 387)

6. A. Agarwal, K. Kang, S. Bhunia, J. Gallagher, and K. Roy, Effectiveness of Dual-Vt Designs in Nano-Scale Technologies under Process Variations, ACM/IEEE International Symposium on Low-Power Electronics and Design, August 2005, pp. 14-19. (no 386)

7. M. Alam, H. Kufluoglu, B. Paul, K. Kang, and K. Roy, On Reliable Circuits and Systems: How Reliability Considerations are Reshaping Oxide Scaling, Device Geometry, and VLSI Algorithm, 2005 IEEE International Conference on Integrated Circuit and Technology, May 2005, pp. 117-122 (no 383)

8. C. Kim, K. Roy, S. Hsu, R. Krishnamurthy and S. Borkar, An On-Die Leakage Current Sensor for Measuring Process Variation in Sub-90nm Generations, 2005 IEEE International Conference on Integrated Circuit and Technology, May 2005, pp. 221-222. ( no 382)

9. A. Datta, S. Mukhopadhyay, S. Bhunia, and K. Roy, Reliability Analysis and Yield Prediction of High Performance Pipelined Circuit with respect to Delay Failures in sub-100nm Technology,IEEE International Symposium on On-Line Testing, 2005. ( no 379)

10. K. Kang, B. Paul, and K. Roy, Statistical Timing Analysis using Levelized Covariance Propagation, IEEE Design and Test in Europe (DATE), pp. 764-769, 2005. (no 371)

11. C.H. Kim, J. Kim, I, Kim, and K. Roy, A Process and Temperature Variation Aware Leakage Reduction Technique with Improved Stability for On-Die Caches, IEEE International Solid-State Circuits Conference, pp. 482-483, February 2005. (no 363)

2004

1. H. Mahmoodi, S. Mukhopadhyay, and K. Roy, Estimation of Delay Variations Due to Random Dopant Fluctuations in Nano-Scaled CMOS Circuits, IEEE Custom Integrated Circuits Conference, Oct. 2004 ( no 349)

2. A. Agarwal, B. Paul, and K. Roy, Process Variation in Nano-Scale Memories: Failure Analysis and Process-Tolerant Architecture, IEEE Custom Integrated Circuits Conference, October 2004. (no 348)

3. S. Choi, B. Paul, and K. Roy, Novel Sizing Algorithm for Yield Improvement under Process Variation in Nanometer Technology, IEEE/ACM Design Automation Conference, pp. 454-459, June 2004. (no 343)

4. S. Mukhopadhyay, H. Mahmoodi-Meimand, and K. Roy, Modeling and Estimation of Failure Probability due to Parameter Variations in Nano-Scaled SRAMs for Yield Enhancement, IEEE 2004 Symposium on VLSI Circuits, pp. 64-67, June 2004. (no 341)

5. C. Kim, K. Roy, S. Hsu, R. Krishnamurthy, and S. Borkar, An On-Die CMOS Leakage Sensor for Measuring Process Variation in Sub-90nm Generation, IEEE 2004 Symposium on VLSI Circuits, pp. 250-251, June 2004. (no 340)

6. A. Agarwal, K. Roy, S. Hsu, R. Krishnamurthy, and S. Borkar, 90nm 6.5GHz 128X64 4-Read 4-Write Ported Parameter Variation Tolerant Register File, IEEE 2004 Symposium on VLSI Circuits, pp. 386-387, June 2004. (no 339)

2003

1. H. Li, C. Cher, T. Vijaykumar, and K. Roy, VSV: L2-Miss-Driven Variable Supply Voltage Scaling for Low-Power, IEEE Micro, pp. 19-28, December 2003.( no 327)

2. H. Suzuki, W. Jeong, and K. Roy, Low Power Adder with Adaptive Supply Voltage, IEEE International Conference on Computer Design, pp. 103-106, 2003. (no 322)

3. S. Mukhopadhyay and K. Roy, Modeling and Estimation of Total Leakage Current in Nano-Scaled CMOS Devices Considering the Effect of Process Variation, IEEE International Symposium on Low-Power Electronics and Design, pp. 172-175, August 2003. (no 315)

4. C. Neau and K. Roy, Optimal Body Bias Selection for Leakage Improvement and Process Compensation over Different Technology Generations, IEEE International Symposium on Low-Power Electronics and Design, pp. 116-121, August 2003. (no 312)

5. C. H. Kim, K. Roy, S. Hsu, A. Alvandpour, R. Krishnamurthy, and S. Borkar, A Process Varia tion Compensating Technique for Sub-90nm Dynamic Circuits, IEEE 2003 Symposium on VLSI Circuits, pp. 205-206, June 2003 (no 308)

6. Y. Im and K. Roy, A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits, IEEE International Symposium on Circuits and Systems, May 2003. (no 305)

7. N. Sirisantana and K. Roy, Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies, IEEE Design and Test in Europe (DATE), 1160-1161, March 2003. (no 300)

8. S. Choi and K. Roy, A New Crosstalk Noise Model for DOMINO Logic Circuits, IEEE Design and Test in Europe (DATE), pp. 1112-1113, March 2003. (no 299)

9. Y. Im and K. Roy, LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits, IEEE International Symposium on VLSI, pp. 45-52, 2003.(no 295)

2002

1. S. Choi, F. Dartu, and K. Roy, Timed Pattern Generation for Noise-on-Delay Calculation, ACM/IEEE Design Automation Conference, June 2002, pp. 870-873. (no 284)

2. S. Choi and K. Roy, Noise Analysis under Capacitive and Inductive Coupling for High Speed Cir-cuits, IEEE International Workshop on Electronic Design, Test, and Applications, Christchurch, New Zealand, January 2002, pp. 365-369.(no 274)

3. S. Zhao, K. Roy, and C.-K. Koh,, Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement, Asia-South Pacific Design Automation Conference/ VLSI Conference, 2002, pp. 489-495 (no 273)

4. S.H. Choi, B. Paul, and K. Roy, Dynamic Noise Analysis with Capacitive and Inductive Coupling in Precharge-Evaluate Circuits, Asia-South Pacific Design Automation Conference/ VLSI Conference, 2002, pp. 65-70. (no 272)

2001

1. Y. Im and K. Roy, CASh: A Novel Clock As Shield Design Methodology for Noise Immune Precharge-Evaluate Logic, IEEE International Conference on Computer-Aided Design, November 2001. (no 270)

2. B. Paul, S.-H. Choi, Y. Im, and K. Roy, Design Verification and Robust Design Technique for Cross-Talk Faults, Asian Test Symposium, November 2001, pp. 449-454. (no 269)

3. S.H. Choi, D. Somasekhar, and K. Roy, Dynamic Noise Model and Its Application to High Speed Circuit Design, IEEE Mixed-Signal Test Workshop, Lake Lanier, Georgia, June 2001. (no 265)

4. S. Zhao, K. Roy, and C.K. Koh, Decoupling Capacitance Allocation for Power Supply Noise Suppression, Internation Symposium on Physical Design, April 2001. (no 258)

2000

1. A. Solomatnikov, D. Somasekhar, and K. Roy, Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family, European Solid-State Circuits Conference, pp 424-427, Sep. 2000.( no 247)

2. S. Zhao, K. Roy, and C. Koh, Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-micron CMOS Circuits, IEEE International Conference on Computer Design, 2000, pp. 65-72. (no 245)

3. D. Somasekhar, S. Choi, K. Roy, Y. Ye, and V. De, Dynamic Noise Immunity in Precharge Evaluate Circuits, ACM/IEEE Design Automation Conf., 2000, pp. 243-246. (no 240)

4. S. Zhao and K. Roy, Estimation of Worst Case Switching Noise on Power Supply Lines in Deep Submicron CMOS Circuits, International Conference on VLSI Design, Jan. 2000, pp. 168-173. (no 234)

Selected_Publications

Conference Papers:

2008

1. S. Ghosh, J.H. Choi, P. Ndai and K. Roy, "O2C: Occasional Two-Cycle Operations for Dynamic Thermal Management in High Performance In-Order Microprocessors," Proc. of the International Symposium of Low Power Electronic Design (ISLPED), August 2008.

Journal Papers:

2007

1. K. Kang, H. Kufluoglu, K. Roy, and M. A. Alam, "Impact of Negative Bias Temperature Instability in Nano-Scale SRAM Array: Modeling and Analysis," accepted for publication in IEEE Transactions on Computer Aided Design.

2. B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam and K. Roy, "Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits," IEEE Transactions on Computer Aided Design, vol. 26, no. 4, April 2007, pp. 743-751.

2005

1. B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam and K. Roy, "Impact of NBTI on the Temporal Performance Degradation of Digital Circuits," IEEE Electron Device Letter, vol. 26, August 2005, pp 560-562.

Conference Papers

2007

1. K. Kang, K. J Kim, Ahmad E Islam, M. Alam, and K. Roy, Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement,accepted in 2007 Design Automation Conference, San Diego, California, USA

2. K. Kang, M. A. Alam, and K. Roy, "Estimation of NBTI Degradation Using On-Chip IDDQ Measurement," IEEE International Reliability Physics Symposium, April 2007, pp. 10-16.

2006

1. B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy, "Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits," Design, Automation and Test in Europe, March 2006, pp. 1-6.

2. K. Kang, M. A. Alam, and K. Roy, "Analysis and Design of Nano-Scale Digital CMOS Circuits under Spatial and Temporal Reliability Degradation," SRC Student Symposium, 2006.

2005

1. M. A. Alam, H. Kufluoglu, B. C. Paul, K. Kang, and K. Roy, "On reliable circuits and systems: how reliability considerations are reshaping oxide scaling, device geometry, and VLSI algorithm," International Conference on Integrated Circuit Design and Technology, May 2005, pp. 117-122.

2. A. Datta, S. Mukhopadhyay, S. Bhunia, and K. Roy, Reliability Analysis and Yield Prediction of High Performance Pipelined Circuit with respect to Delay Failures in sub-100nm Technology, IEEE International Symposium on On-Line Testing, 2005.

Selected_Publications

Journal Papers:

2008:

1. Q. Chen, N. N. Mojumder, K. Roy, "Modeling and Analysis of the Asymmetric Source/Drain Extension CMOS Transistors for Nanoscale Technologies," IEEE Transactions on Electron Devices, Volume 55, Issue 4, April 2008, pp. 1005-1012

2007:

1. A. Agarwal, K. Kang, S. Bhunia, J. D. Gallagher and K. Roy, "Device-Aware Yield-Centric Dual-Vt Design under Parametric Variations in Nano-Scale Technologies," accepted for publication in IEEE Transactions on VLSI.

2. A. Bansal, S. Mukhopadhyay and K. Roy, "Device Optimization Technique for Robust and Low Power FinFET SRAM Design in Nanoscale Era," To appear in IEEE Transactions on Electron Devices, June 2007.

3. A. Bansal and K. Roy, "Analytical Sub-threshold Potential Distribution Model for Gate Underlap Double-Gate MOS Transistors," To appear in IEEE Transaction on Electron Devices, July 2007.

4. A. Datta, A. Goel, T. Cakici, H. Mahmoodi-Meimand, D. Lekshmanan and K. Roy, "Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices," to appear at IEEE Transactions of Computer-Aided Design (TCAD).

2006:

1. A. Bansal, B. Paul and K. Roy, "An Analytical Capacitance Model for Interconnects using Conformal Mapping," In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Dec. 2006, pp. 2765-2774.

2. B. Paul, A. Bansal and K. Roy, "Underlap DGMOS for Ultra-Low Power Digital Sub-threshold Operation," IEEE Transactions on Electron Devices, April 2006, pp. 910-913.

4. H. Ananthan and K. Roy, "Technology and Circuit Design Considerations in Width-Quantized Quasi-Planar Double-Gate SRAM," IEEE Transactions on Electron Devices, February 2006, pp 242-250.

5. J. Kim and K. Roy, "A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies," IEEE Transactions on VLSI Systems, May 2006, pp. 549-552.

6. S. Mukhopadhyay, H. Mahmoodi-Meimand, and K. Roy, "A Novel High-Performance and Robust Sense Amplifier Using Independent Gate Control in Sub-50nm Double-Gate MOSFET," IEEE Transactions on VLSI Systems, February 2006, pp. 183-192.

7. S. Mukhopadhyay, K. Kim, C.-T. Chuang, and K. Roy, "Modeling and Analysis of Total Leakage Currents in Nano-scale Double Gate Devices and Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits, October 2006, pp. 2052-2061.

8. S. Mukhopadhyay, K. Kim, X. Wang, D. Frank, P. Oldiges, C.-T. Chuang, and K. Roy, "Optimal Ultra-Thin Body FD/SOI Device Structure Using Thin-BOX for Sub-50nm SRAM Design," Vol. 27, Issue 4, April 2006, pp. 284-287.

9. S. Mukhopadhyay, S. Bhunia, and K. Roy, "Modeling and Analysis of Loading Effect on Leakage of Nano-Scale Bulk CMOS Logic Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits, August 2006, pp. 1486-1495.

2005:

1. A. Agarwal, S. Mukhopadhyay, C.H. Kim, A. Raychowdhury, and K. Roy, "Leakage Power Analysis and Reduction: Models, Estimation and Tools," IEEE Proceedings -- Computers and Digital Techniques, May 2005, pp. 353-368.

2. A. Bansal, B. Paul and K. Roy, "Modeling and Optimization of Fringe Capacitance of Nanoscale DGMOS Devices," IEEE Transactions on Electron Devices, Feb. 2005, pp. 256-262.

3. A. Bansal and K. Roy, "Asymmetric Halo CMOSFET to Reduce Static Power Dissipation with Improved Performance," IEEE Transactions on Electron Devices, March 2005, pp. 397-405.

4. C. H. Kim, J. Kim, S. Mukhopadhyay, and K. Roy, "A Forward Body-Biased Low-Leakage SRAM Cache: Device, Circuit, and Architecture Considerations," IEEE Transactions on VLSI systems, March 2005, pp. 348-357.

5. S. Mukhopadhyay, A. Raychowdhury, and K. Roy, "Accurate Estimation of Total Leakage in Nanometer Scale Bulk CMOS Circuits Based on Device Geometry and Doping Profile," IEEE Transactions on CAD of Integrated Circuits, March 2005, pp. 363-381.

2004:

1. H. Mahmoodi-Meimand and K. Roy, "Diode-Footed Domino: A Leakage-Tolerant High Fan-in Dynamic Circuit Design Style," IEEE Transaction on Circuits and Systems: I, pp. 495-503, March 2004.

2. J. Kim and K. Roy, "Double-Gate MOSFET Subthreshold Circuit for Ultralow Power Applications," IEEE Transactions on Electron Devices, pp. 1468-1474 September 2004.

2003:

1. A. Agarwal, H. Li, and K. Roy, "DRG Cache: A Data Retention Gated Ground Cache for Low Power Applications," IEEE Journal of Solid-State Circuits, pp. 319-328, February 2003.

2. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicron CMOS Circuits," IEEE Proceedings, pp. 305-327, February 2003.

3. S. Mukhopadhyay, C. Neau, T. Cakici, A. Agarwal, C. H. Kim, and K. Roy, "Gate Leakage Reduction for Scaled Devices Using Transistor Stacking," IEEE Transactions on VLSI Systems, Aug. 2003, pp. 716-730.

2002:

1. L. Wei, R. Zhang, K. Roy, Z. Chen, and D. Janes, "Vertically Integrated SOI Circuits for Low-Power and High-Performance Applications," IEEE Transactions on VLSI Systems, June 2002, pp. 351-362.

2. R. Zhang and K. Roy, "Low-Power High-Performance Double-Gate Fully Depleted SOI Circuit Design," IEEE Transactions on Electron Devices, May 2002, pp. 852-862.

3. R. Zhang, K. Roy, C. Koh, and D. Janes, "Exploring SOI Device Structures and Interconnect Architectures for Low-Power High-Performance Circuits," IEEE Proceedings: Computers and Digital Techniques, Vol. 149, Issue 04, July 2002, pp. 137-145.

Conference Papers:

2007:

1. A. Bansal, J. Kim, K. Kim, S. Mukhopadyay, C.-T. Chuang and K. Roy, "High-Performance Device Optimization and Dual-VT Technology Options for DoubleGate FET," ICICDT 2007.

2. A. Bansal, J. Kim, K. Kim, S. Mukhopadyay, C.-T. Chuang and K. Roy, "Optimal Dual-Vt Design beyond 65nm Technology Node," ACEED 2007.

3. D. Lekshmanan, "Body thickness optimization and sensitivity analysis for high performance FinFETs" , DRC 2007

4. T. Cakici, K. Kim, and K. Roy, "FinFET Based SRAM Design for Low Standby Power Applications," IEEE ISQED 2007.

2006:

1. H. Ananthan, and K. Roy, "A Fully Physical Model for Leakage Distribution under Process Variations in Nanoscale Double-Gate CMOS," IEEE/ACM Design Automation Conference (DAC), July 2006.

2. Q. Chen, S. Mukhopadhyay, A. Bansal, and K. Roy, "Circuit-aware Device Design Methodology for Nanometer Technologies: A Case Study for Low Power SRAM Design," proceedings of IEEE Design Automation and Test in Europe (DATE), March 2006.

3. S. Gangwal, S. Mukhopadhyay and K. Roy, "Optimization of Surface-orientation for high performance, low power and robust FinFET SRAM," CICC 2006.

4. T. Cakici, B. Jung, and K. Roy, "High Q and High Tuning Range FinFET Based Varactors for Low Cost SoC Integration," IEEE International SOI Conference, Oct. 2006, pp. 67-68.

2005:

1. A. Agarwal, K. Kang, and K. Roy, "Accurate Estimation and Modeling of Total Chip Leakage Considering Inter- & Intra-Die Process Variations," IEEE International Conference on Computer-Aided Design, November 2005, pp. 736-742.

2. A. Agarwal, K. Kang, S. Bhunia, J. D. Gallagher, and K. Roy, "Effectiveness of Low Power Dual-Vt Designs in Nano-Scale Technologies Under Process Parameter Variations," International Symposium on Low Power Electronics and Design, August 2005, pp. 14-19.

3. A. Agarwal, K. Kang, S. Bhunia, J. Gallagher, and K. Roy, "Effectiveness of Dual-Vt Designs in Nano-Scale Technologies under Process Variations," ACM/IEEE International Symposium on Low-Power Electronics and Design, August 2005, pp. 14-19.

4. A. Bansal, S. Mukhopadhyay and K. Roy, "Modeling and Optimization Approach to Robust and Low-Power FinFET SRAM Design in Nanoscale Era," Proc. of the IEEE Custom Integrated Circuits Conference (CICC), 2005, pp. 835-838.

5. A. Bansal and K. Roy, "Asymmetric Halo CMOSFET to Reduce Static Power Dissipation with Improved Performance," Proc. of the Int. Sym. Ckts And Sys., 2005, pp. 1-4.

6. B. Paul, A. Bansal and K. Roy, "Underlap DGMOS for Ultra-low Power Digital Sub-threshold Operation," Accepted for publication in the Device Research Conference, 2005, pp. 227-228.

7. H. Ananthan and K. Roy, "Technology-Circuit Co-Design in Width-Quantized Quasi-Planar Double-Gate SRAM," 2005 IEEE International Conference on Integrated Circuit and Technology, May 2005, pp. 155-160.

8. H. Ananthan, A. Bansal, and K. Roy, "Analysis of Drain-to-Body Band-To-Band Tunneling in Double-Gate MOSFET," IEEE SOI Conference, October 2005.

9. K. Roy, H. Mahmoodi-Meimand, S. Mukhopadhyay, A. Bansal, H. Ananthan, and T. Cakici, "Double-Gate SOI Devices for Low-Power and High-Performance Applications," IEEE International Conference on Computer-Aided Design (ICCAD), November 2005, Invited Paper.

10. S. Hsu, A. Agarwal, K. Roy, R. Krishnamurthy, and S. Borkar, "An 8.3 GHz Dual Supply/Threshold Optimized 32b Integer ALU-Register File Loop in 90nm CMOS," ACM/IEEE International Symposium on Low-Power Electronics and Design, August 2005, pp. 103-106.

11. S. Mukhopadhyay, K. Kang, H. Mahmoodi-Meimand, and K. Roy, "Design of Reliable and Self-Repairing SRAM in Nano-scale Technologies using Leakage and Delay Monitoring," IEEE International Test Conference, November 2005, pp. 1126-1135.

12. S. Mukhopadhyay, H. Mahmoodi-Meimand, and K. Roy, "Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET," IEEE International Symposium on Quality Electronic Design, pp.490-495, 2005.

13. S. Mukhopadhyay, K. Kim, C.-T. Chuang, and K. Roy, "Modeling and Analysis of Gate Leakage in Ultra-Thin Oxide sub-50nm Double Gate Devices and Circuits," IEEE International Symposium on Quality Electronic Design, pp. 410-415, 2005.

14. S. Mukhopadhyay, K. Kim, C.-T. Chuang, and K. Roy, "Modeling and Analysis of Total Leakage Currents in Nanoscale Double Gate Devices and Circuits," ACM/IEEE International Symposium on Low-Power Electronics and Design, August 2005, pp. 8-13.

15. S. Mukhopadhyay, S. Bhunia, and K. Roy, "Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits," IEEE Design and Test in Europe (DATE), pp. 224-229, 2005.

16. T. Cakici, H. Mahmoodi-Meimand, S. Mukhopadhyay and K. Roy,"Independent Gate Skewed Logic in Double-Gate SOI Technology," IEEE International SOI Conference, Oct. 2005, pp. 83-84.

2004:

1. A. Bansal, B. Paul and K. Roy, "Impact of Underlap on Gate Capacitance and Gate Tunneling Current in 16nm DGMOS Devices," Proceedings of the IEEE International SOI Conference, 2004, pp. 94-95.

2. A. Raychowdhury, S. Mukhopadhyay, and K. Roy, "Modeling and Estimation of Leakage in Sub-90nm Devices," IEEE VLSI Conference, January 2004. Embedded Keynote Paper.

3. A. Agarwal, B. Paul, and K. Roy, "Process Variation in Nano-Scale Memories: Failure Analysis and Process-Tolerant Architecture," IEEE Custom Integrated Circuits Conference, October 2004.

4. A. Agarwal, C. H. Kim, S. Mukhopadyay, and K. Roy, "Leakage in Nano-Scale Technologies: Mechanisms, Impact, and Design Considerations," IEEE/ACM Design Automation Conference, pp. 6-11, June 2004, Invited Paper.

5. A. Agarwal, K. Roy, S. Hsu, R. Krishnamurthy, and S. Borkar, "90nm 6.5GHz 128X64 4-Read 4-Write Ported Parameter Variation Tolerant Register File," IEEE 2004 Symposium on VLSI Circuits, pp. 386-387, June 2004.

6. C. H. Kim, H. Ananthan, J. Kim, and K. Roy, "Effectiveness of Using Supply Voltage as Back-Gate Bias in Ground Plane SOI MOSFETs," IEEE International SOI Conference, pp. 69-70, Oct. 2004.

7. H. Ananthan, A. Bansal, and K. Roy, "FinFET SRAM -- Device and Circuit Design Considerations," IEEE International Conference on Quality IC Design, pp. 511-516, March 2004.

8. H. Ananthan, C. H. Kim, K. Roy, "Larger-than-Vdd forward body bias in sub-0.5V nanoscale CMOS," IEEE International Symposium on Low-Power Electronics and Design, pp. 8-13, August 2004.

9. H. Mahmoodi-Meimand, S. Mukhopadhyay, and K. Roy, "High Performance and Low Power Domino Logic Using Independent Gate Control in Double-Gate SOI MOSFETs," IEEE International SOI Conference, pp. 67-68, Oct. 2004.

2003:

1. A. Agarwal and K. Roy, "A Noise Tolerant Cache Design to Reduce Gate and Subthreshold Leakage in the Nanometer Regime," IEEE International Symposium on Low-Power Electronics and Design, pp. 18-21, August 2003.

2. C. H. Kim, J. Kim, S. Mukhopadhyay, and K. Roy, "A Forward Body-Biased Low-Leakage SRAM Cache: Device and Architecture Considerations," IEEE International Symposium on Low-Power Electronics and Design, pp. 6-9, August 2003.

3. C. Neau and K. Roy, "Optimal Body Bias Selection for Leakage Improvement and Process Compensation over Different Technology Generations," IEEE International Symposium on Low-Power Electronics and Design, pp. 116-121, August 2003.

4. H. Mahmoodi-Meimand and K. Roy, "Data-Retention Flip-Flops for Power-Down Applications," IEEE International Symposium on Circuits and Systems, May 2003.

5. H. Mahmoodi-Meimand and K. Roy, "Dual-Edge Triggered Level Converting Flip-Flops," IEEE International Symposium on Circuits and Systems, May 2003.

6. J. Kim and K. Roy, "Double Gate MOSFET Subthreshold Logic for Ultra-Low Power Applications," IEEE International SOI Conference, pp. 97-98, October 2003.

7. S. Mukhopadhyay and K. Roy, "Modeling and Estimation of Total Leakage Current in Nano-Scaled CMOS Devices Considering the Effect of Process Variation," IEEE International Symposium on Low-Power Electronics and Design, pp. 172-175, August 2003.

8. S. Mukhopadhyay, A. Raychowdhury, and K. Roy, "Accurate Estimation of Total Leakage Current in Scaled CMOS Logic Circuits Based on Compact Current Modeling,'' IEEE/ACM Design Automation Conference, pp. 169-174, June 2003.

9. T. Cakici, A. Bansal and K. Roy, "A Low Power Four Transistor Schmitt Trigger for Asymmetric Double Gate FullyDepleted SOI Devices," IEEE International SOI Conference, Oct. 2003, pp. 21-22.

2002:

1. A. Agarwal, H. Hai, and K. Roy, "DRG-Cache: A Data Retention Gated-Ground Cache for Low Power," ACM/IEEE Design Automation Conference, June 2002, pp. 473-478.

2. H. Mahmoodi-Meimand and K. Roy, "Self-Precharging Flip-Flop (SPFF): A New Level Converting Flip-Flop," European Solid-State Circuits Conference (ESSCIRC), September 2002, pp. 407-410.

3. J. Kim and K. Roy, "Sense-Amplifierless DCSL:A Circuit Style Tolerant to Folating Body Effects in PD/SOI," European Solid-State Circuits Conference (ESSCIRC), September 2002, pp. 271-274.

4. J. Kim and K. Roy, "SOI-Specific Tri-State Inverter and Its Application," IEEE International SOI Conference, pp. 145-146, 2002.

5. J. Kim, R. Joshi, C. Chuang, and K. Roy, "SOI-Optimized 64bit High-Speed CMOS Adder Design," IEEE VLSI Circuits Symposium, June 2002.

6. T. Cakici and K. Roy, "Current Mirror Evaluation Logic: A New Circuit Style for High

Fan-in Dynamic Gates," ESSCIRC 2002, pp. 395-398.

2001:

1. J. Kim and K. Roy, "A Leakage Tolerant High Fan-in Dynamic Circuit Design Technique," European Solid State Circuits Conference, September 2001.

2. R. Zhang, K. Roy, D. Janes, and C. Koh, "Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration," ACM/IEEE Design Automation Conference, 2001, pp. 846-851.

3. R. Zhang, K. Roy, and D. Janes, "Double-Gate Fully-Depleted SOI Transistors for Nano-Technology Regime," ACM/IEEE International Symposium on Low Power Electronics and Design, Aug. 2001, pp. 213-218.

Selected_Publications

Journal Publications:

2006

1. S. Ghosh, S. Bhunia, A. Raychowdhury and K. Roy, A novel delay fault testing methodology using low-overhead built-in delay sensor, IEEE Trans. Computer Aided Design, Dec 2006.

2005

1. Q. Chen, H. Mahmoodi, S. Bhunia, and K. Roy, Efficient Testing of SRAM with Optimized March Sequences and a Novel DFT Technique for Emerging Failures due to Process Variations, IEEE Trans. on VLSI, Dec. 2005.

2. S. Bhunia, H. Mahmoodi, S. Mukhopadhyay, D. Ghosh and K. Roy, Low-Power Scan Design Using First Level Supply Gating, IEEE Transactions on Very Large Scale Integration Systems (TVLSI), pp. 384-395, March, 2005.

3. S. Bhunia and K. Roy, Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current, Journal of Electronic Testing: Theory and Applications, pp. 147-159, 2005.

4. S. Mukhopadhyay, H. Mahmoodi and K. Roy, Modeling of Failure Probability and Statistical Design of SRAM Array for Yield Enhancement in Nano-Scaled Technologies, IEEE Transactions on Computer-Aided Design of Integrated Circuits, pp. 1859-1880, Dec. 2005.

2004

1. N. Sirisantana, B. Paul, and K. Roy, Enhancing yield at the end of the technology roadmap, IEEE Design and Test, pp. 563-571, Nov.- Dec. 2004.

2003

1. A. Keshavarzi, K. Roy, C. Hawkins, and V. De, Multiple-Parameter CMOS IC Testing with Increased Sensitivity for IDDQ, IEEE Transactions on VLSI Systems, pp. 863-870, Oct. 2003.

2002

1. Z. Chen, L. Wei, A. Keshavarzi, and K. Roy, IDDQ Testing for Deep Sub-Micron IC's: Challenges and Solutions, IEEE Design and Test, pp. 24-33, March-April, 2002.

2. A. Keshavarzi, K. Roy, J. Tschantz, S. Narendra, A. Daasch, C. Hawkins, and V. De, Impact of Leakage and Process Variation on Current-Based Testing for Future

Scaled CMOS Circuits, IEEE Design and Test, pp. 36-43, Sep.-Oct., 2002.

2001

1. A. Keshavarzi, K. Roy, and C. Hawkins, Intrinsic Leakage in Deep Submicron IC's -- Measurement Based Test and Power Solutions, IEEE Design and Test, pp. 42-49, Jan.-Feb., 2001.

2. Z. Chen, L. Wei, and K. Roy, On Effective IDDQ Testing of Low Voltage CMOS Circuits Using Leakage Control Techniques, IEEE Transactions on VLSI Systems, pp. 718-725, Oct. 2001.

2000

1. X. Zhang, K. Roy, and S. Bhawmik, Low Power Weighted Random Pattern Testing, IEEE Transactions on Computer-Aided-Design, pp. 1363-1369, Nov. 2000.

2. K. Muhammad and K. Roy, Fault Detection and Location Using IDD Waveform Analysis, IEEE Transactions on Computer-Aided-Design, pp. 1389-1398, Nov. 2000.

Conference Publications:

2007

1. S. Ghosh, S. Bhunia, and K. Roy, A Fault Tolerant Technique for Improved Yield in Nanometer Technologies by Adaptive Clock Stretching, International On-Line Test Symposium, 2007.

2006

1. S. Ghosh, S. Mukhopadhyay, K. Kim and K. Roy, Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM, Design Automation Conference, 2006.

2. S. Ghosh, S. Bhunia, A. Raychowdhury and K. Roy, Delay fault localization in test-per-scan BIST using Built-in Delay Sensor, International On-Line Testing Symposium, 2006.

3. A. Goel, S. Bhunia, H. Mahmoodi and K. Roy, A Low-Overhead Design of Soft-Error-Tolerant Scan Flip-Flop with Enhanced-Scan Capability, ASP-DAC, 2006.

4. S. Mukhopadhyay, A. Agarwal, Q. Chen and K. Roy, SRAMs in Scaled Technologies under Process Variations: Failure Mechanisms, Test & Variation Tolerant Design, IEEE Custom Integrated Circuits Conference, Sep. 2006. [Invited Paper]

2005

1. Q. Chen, H. Mahmoodi, S. Bhunia, and K. Roy, Modelling and Testing of SRAM for New Failure Mechanisms due to Process Variations in Nanoscale CMOS, proceedings of IEEE VLSI Test Symposium (VTS), May 2005.

2. S. Ghosh, S. Bhunia and K. Roy, Shannon expansion based supply-gated logic for improved power and testability, Asian Test Symposium, 2005.

3. M. Meterelliyoz, H. Mahmoodi and K. Roy, A Leakage Control System for Thermal Stability During Burn-In Test, International Test Conference (ITC), 2005.

4. S. Mukhopadhyay, K. Kang, H. Mahmoodi and K. Roy, Design of Reliable and Self-Repairing SRAM in Nano-scale Technologies using Leakage and Delay Monitoring, International Test Conference (ITC), 2005.

5. P. Ndai, A. Agarwal, Q. Chen and K. Roy, A Soft Error Monitor Using Current Switching Detection (in SRAM) , ICCD 2005.

6. A. Raychowdhury, S. Ghosh and K. Roy, A Novel On-chip Delay Measurement Hardware for Efficient Speed-Binning, International On-Line Testing Symposium, 2005.

7. A. Raychowdhury, S. Ghosh, S. Bhunia, D. Ghosh and K. Roy, "A Novel Delay Fault Testing Methodology using Low-overhead Built-in Delay Sensor, European Test Symposium, 2005.

8. S. Bhunia, H. Mahmoodi, and K. Roy, Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Patitioning, IEEE International Symposium on Quality Electronic Design, pp.453-458, 2005.

9. S. Bhunia, H. Mahmoodi, A. Raychowdhury, and K. Roy, A Novel Low-Overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application, IEEE Design and Test in Europe (DATE), pp.1136-1141, 2005.

2004

1. S. Bhunia, H. Mahmoodi, S. Mukhopadhyay, D. Ghosh and K. Roy, A Novel Low Power Scan Design Technique Using Supply Gating, ICCD, 2004, [Best Paper Award].

2. S. Bhunia, A. Raychowdhury, and K. Roy, Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current, IEEE International Conference on Quality IC Design, pp. 389-394, March 2004.

3. S. Mukhopadhyay, H. Mahmoodi-Meimand, and K. Roy, Modeling and Estimation of Failure Probability due to Parameter Variations in Nano-Scaled SRAMs for Yield Enhancement, IEEE 2004 Symposium on VLSI Circuits, pp. 64-67, June 2004.

2003

1. S. Bhunia and K. Roy, Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Current, 4th IEEE Latin American Test Workshop, pp. 183-187, February 2003. [Best Paper Award]

2. K. Roy, T.M. Mak, and K.-T. Cheng, Test Considerations for Nanometer Scale CMOS Circuits, IEEE VLSI Test Symposium, May, 2003. [Invited Paper]

3. D. Ghosh, S. Bhunia, and K. Roy, Multiple Scan Chain Design Technique for Power Reduction During Test Application in BIST, 18th International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 191-198, 2003.

2002

1. Z. Chen, L. Wei, A. Keshavarzi, and K. Roy, IDDQ Testing for Deep Submicron CMOS ICs: Challenges and Solutions, IEEE Latin America Test Workshop, Feb. 2002.

2. S. Bhunia and K. Roy, Fault Detection and Diagnosis Using Wavelet Based Transient Current Analysis, Design Automation and Test in Europe (DATE), pp. 1118, March, 2002.

3. S. Bhunia and K. Roy, Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform, IEEE VSLI Test Symposium, pp. 302 -307, April, 2002.

4. S. Bhunia, K. Roy, and J. Segura, A Novel Wavelet Transform Based Transient Current Analysis for Fault Detection and Localization, ACM/IEEE Design Automation Conference, pp. 361-366, June, 2002.

5. S. Bhunia, H. Li, and K. Roy, A High Performance IDDQ Testable Cache for Scaled CMOS Technologies, IEEE Asian Test Symposium, pp. 157-162, November, 2002.

2001

1. B. Paul, S.-H. Choi, Y. Im, and K. Roy, Design Verification and Robust Design Technique for Cross-Talk Faults, Asian Test Symposium, pp. 449-454, November, 2001.

2000

1. Z. Chen, L. Wei, and K. Roy, On Effective IDDQ Testing of Low-Voltage CMOS Circuits Using Leakage Control Techniques, IEEE International Symposium on Quality of IC Design, pp. 181-188, 2000. [Best Paper Award]

2. X. Zhang and K. Roy, Low-Power BIST with Peak Power Vector Elimination, International Symposium on Quality of IC Design, pp. 425-432, 2000.

3. K.-T. Cheng, S. Dey, M. Rodgers, and K. Roy, Test Challenges for Deep Submicron Technologies, ACM/IEEE Design Automation Conference, pp. 142-149, 2000. [Invited Embedded Tutorial]

4. X. Zhang and K. Roy, Power Reduction in Test-Per-Scan BIST, IEEE International On-Line Test Workshop, pp. 133-138, 2000.

5. A. Keshavarzi, K. Roy, M. Sachdev, C. Hawkins, K. Soumyanath, and V. De, Multiple-Parameter CMOS IC Testing with Increased Sensitivity for IDDQ, IEEE International Test Conference, pp. 1051-1059, 2000.

Selected_Publications

Journal Publications:

2005

1. A.Raychowdhury, B. Paul, S. Bhunia, and K. Roy, Computing with Subthreshold Leakage: Device/Circuit/Architecture Co-Design for Ultralow-Power Subthreshold Operation, IEEE Transactions on VLSI Systems, November 2005, pp. 1213-1224 (no. 105)

1. B. Paul, A. Raychowdhury, and K. Roy, Device Optimization for Digital Subthreshold Logic Operation, IEEE Transactions on Electron Devices, February 2005, pp. 237-247. (no. 87)

2004

1. J. Kim and K. Roy, Double-GateMOSFET Subthreshold Circuit for Ultralow Power Applications,IEEE Transactions on Electron Devices, pp. 1468-1474 September 2004. (no. 82)

2003

1. C. H. Kim, H. Soeleman, and K. Roy, "Ultra-Low Power DLMS Adaptive Filter for Hearing Aid Applications", IEEE Transactions on VLSI Systems, pp. 1058-1067, December 2003 (no. 76)

O 2005 IEEE Circuits and Systems Society Outstanding Young Author Award

2001

1. H. Soeleman, K. Roy, and B. Paul, "Robust Sub-Threshold Logic for Ultra-Low Power Operation", IEEE Transactions on VLSI Systems, Special issue on low-power design, pp.90-99, February 2001.(no. 52)

Conference Publications:

2006

1. B. Paul, and K. Roy, Optimizing Oxide Thickness for Digital Sub-threshold Operation, IEEE Device Research Conference, 2006, pp. 63-64. (no 423)

2. A. Raychowdhury, B. Paul, S. Bhunia, and K. Roy, Computing With Subthreshold Leakage: A Comparative Study of Bulk and SOI Technologies, IEEE Design and Test in Europe (DATE), March 2006(no. 412)

2005

1. A.Raychowdhury, S. Mukhopadhyay, and K. Roy, "A Feasibility Study of Subthreshold SRAM Across Technology Generations", IEEE International Conference on Computer Design (ICCD), October 2005.(no. 395)

2004

1. B.C. Paul, A. Raychowdhury, K. Roy, Device Optimization for Ultra-Low Power Digital Sub-Threshold Operation, IEEE International Symposium on Low-Power Electronics and Design, pp.96-101, August 2004. (no. 359)

2. B. Paul and K. Roy, "Device Optimization for Digital Sub-threshold Operation", IEEE Device Research Conference, pp. 113-114, June 2004. (no. 345)

2003

1. J. Kim and K. Roy, "Double-Gate MOSFET Subthreshold Circuit for Ultralow Power Applications", IEEE Transactions on Electron Devices, pp. 1468-1474, September 2004.(no. 323)

2001

1. B. Paul, H. Soeleman, and K. Roy, "An 8X8 Sub-Threshold Digital CMOS Carry Save Array Multiplier", European Solid State Circuits Conference, September 2001.

2. H. Soeleman and K. Roy, "Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Logic", IEEE International Conference on VLSI Design, pp. 211-214, 2001.

2000

1. H. Soeleman, K. Roy, and B. Paul, "Robust Ultra-Low Power Sub-threshold DTMOS Logic", IEEE International Symposium on Low-Power Electronics and Design, pp. 25-30, 2000

2. H. Soeleman and K. Roy, "Digital CMOS Logic Operation in the Sub-Threshold Region", IEEE Great Lakes Symposium on VLSI, pp. 107-112, March 2000.

Patents:

1. J. Kim and K. Roy, "Double Gate MOSFET Subthreshold Circuit for Ultralow Power Applications", US Patent Pending

2. J. P. Kulkarni and K. Roy SRAM cell with built-in process tolerance patent filed with Purdue Research Foundation, March 2007