Next-Generation Interconnect Materials for 3D Heterogeneous Integration
Description
As semiconductor manufacturing faces diminishing returns, 3D heterogeneous integration (3D-HI) has emerged as a performance booster due to shorter interconnects with reduced latency, ability to combine many functions, and cost savings driven by system architectures. For advanced packaging, interconnect scaling is a key driving factor to enable 3D-HI for increased functionality, improved performance, reduced power loss, increased yield and reliability, and reduced overall costs. The interconnect density increases exponentially for 3D-HI and requires chip-to-substrate microbump pitch below 5m and half-line pitch below 1 m for Cu redistribution layer (RDL). State-of-art 3D stacked integrated circuits do not yet offer these interconnect densities at substrate or package level but can only be achieved with die-to-wafer (D2W) or wafer-to-wafer (W2W) bonding approaches. Hybrid bonding enables high density 3D stacking technology; however, the high thermal budget of the process is a key bottleneck. Further, electromigration related failures of void migration, void accumulation and growth are also critical for hybrid bonded microbumps, significantly dependent on the dielectric/metal interface properties. This project will develop high throughput experimentation with metal, passivation, liner/barrier and dielectric materials to enable low temperature chip-to-substrate high density interconnects. Deposition, planarization, dielectric activation and bonding parameters will be optimized for reliable high-density interconnects.
Start Date
July 2026
Postdoc Qualifications
• Ph.D. in Materials Science, Chemistry, Chemical Engineering, Physics, Electrical Engineering, or a closely related field with a focus in electronic materials processing. The degree must be completed by the appointment start date.
• Demonstrated hands-on cleanroom fabrication experience specifically photolithography, chemical mechanical planarization, surface preparation and activation.
• Experience with electrical test structures and reliability testing including electromigration test and analysis.
• Excellent written and verbal communication skills, as demonstrated by a strong publication record and the ability to present research clearly at conferences.
• Ability to mentor graduate and undergraduate students.
Co-advisors
Shubhra Bansal, Associate Professor, School of Mechanical Engineering, School of Materials Engineering, Purdue University, West Lafayette IN
Xinghang Zhang, Professor, School of Materials Engineering, Purdue University, West Lafayette IN