microchip iconTheme 2: Neuromorphic Fabrics

In our second research theme, we will develop neuromorphic hardware to demonstrate orders of magnitude energy-efficiency improvement in cognitive platforms from the edge of the cloud to the server back-end.


State-of-the-art: GPUs, many-core accelerators, FPGAs

  • Spatial (floating, fixed point) information representation
  • Bulk-synchronous computation
  • Separate processing and memory (Von-Neumann architecture)
  • Synaptic plasticity (memory update)
  • Dense & regular interconnectivity patterns
  • Precise & deterministic hardware
  • General-purpose memory system


Future Neuromorphic Fabrics

  • Time-based and stochastic information representation
  • Event-driven massively parallel computation
  • Computing-in-memory
  • Synaptic and structural plasticity (reconfigurable)
  • Sparse and irregular interconnectivity patterns
  • Emerging (approximate, stochastic) hardware
  • Memory system optimized for synaptic storage

Fig. 2.1: Key attributes of neuromorphic fabrics that will be developed in Theme 2

Fig 2.1 summarizes the key attributes of the neuromorphic fabrics that we will explore vis-à-vis the current state-of-the-art such as GPU, TPU, and other many-core accelerators for machine learning. Our research will demonstrate outcomes in both the software environment and hardware prototypes, including test chips with CMOS designs in post-CMOS technologies (e.g., resistive memory) as well as FPGA prototypes. To address these challenges, we will pursue the following tasks: 2.1: Hardware Primitives; 2.2: Hardware Fabrics; and 2.3: Programming and Evaluation Framework.

Theme Leader

Principal Investigators (PIs)