Yu (Kevin) Cao


Yu Cao

Kevin Cao joined the ASU faculty in 2004. After obtaining his Ph.D. degree, he conducted post-doctoral research at the Berkeley Wireless Research Center (BWRC). At the BWRC center, his research focused on circuit techniques and design methodologies to improve the reliability of VLSI systems under increasing parametric variations and ultra-low power design for computation and communication. He has one patent and has published over 70 journal and conference papers and the book, Nana-CMOS Circuit and Physical Design. Expertise: Compact modeling for nanoscale CMOS and post-silicon technologies, Physical-level design and tools for variability and reliability, Reliable integration of emerging technologies, Low-power design solutions, high-speed interconnect and signaling techniques.


  1. Y. Cao, Predictive Technology Model for Robust Nanoelectronic Design, Springer, 2011.
  2. B. Wong, A. Mittal, Y.Cao, G. Starr, Nano-CMOS Circuit and Physical Design, John Wiley & Sons, Inc., 2004.
  3. D. Kadetotad, Z. Xu, A. Mohanty, P.-Y. Chen, B. Lin, J. Ye, S. Vrudhula, S. Yu, Y. Cao, J. Seo, "Parallel architecture with resistive cross point array for dictionary learning acceleration", IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Special Issue on Solid-State Memristive Devices and Systems, vol. 5, no. 2, pp. 194-204, 2015.
  4. Y.Cao, J. Velamala, K. Sutaria, M. S.-W. Chen, J. Ahlbin, I. S. Esqueda, M. Bajura, M. Fritze, "Cross-layer modeling and simulation of circuit reliability," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 1, pp. 8-23, January 2014.
  5. J. Suh, N. Suda, C. Xu, N. Hakim, Y. Cao, B. Bakkaloglu, "Programmable analog device array (PANDA): a methodology for transistor-level analog emulation," IEEE Transactions on Circuits and Systems I, vol. 60, no. 6, pp. 1369-1380, June 2013.
  6. Z. Xu, M. Cavaliere, P. An, S. Vrudhula, Y. Cao, "The stochastic loss of spikes in Spiking Neural P systems: Design and implementation of reliable arithmetic circuits," Fundamenta Informaticae, vol. 134, no. 1-2, pp. 183-200, 2014.
  7. Z. Xu, C. Yang, M. Mao, K. Sutaria, C. Chakrabarti, Y.Cao, "Compact modeling of STT-MTJ devices," Solid-State Electronics, Elsevier Ltd., Special Issue on the 2013 European Solid-State Device Research & Circuits Conference, vol. 102, pp. 76-81, December 2014.
  8. Z. Xu, A. Mohanty, P.-Y. Chen, D. Kadetotad, B. Lin, J. Ye, S. Vrudhula, S. Yu, J. Seo, Y. Cao, "Parallel programming of resistive cross-point array for synaptic plasticity," Procedia Computer Science, Elsevier Ltd., 5th Annual International Conference on Biologically Inspired Cognitive Architectures, vol. 41, pp. 126-133, November 2014.
  9. C. Yang, Y. Emre, Z. Xu, H. Chen, Y.Cao, C. Chakrabarti, "A low cost multi-tiered approach to improving the reliability of multi-level cell PRAM," Journal of Signal Processing Systems, Elsevier Ltd., vol. 76, no. 2, pp. 133-147, August 2014.
  10. J. B. Velamala, K. B. Sutaria, H. Shimuzu, H. Awano, T. Sato, G. Wirth, Y.Cao, "Compact modeling of statistical BTI under trapping/detrapping," IEEE Transactions on Electron Devices, vol. 60, no. 11, pp. 3645-3654, November 2013.

Yu (Kevin) Cao


Yu Cao

Kevin Cao joined the ASU faculty in 2004. After obtaining his Ph.D. degree, he conducted post-doctoral research at the Berkeley Wireless Research Center (BWRC). At the BWRC center, his research focused on circuit techniques and design methodologies to improve the reliability of VLSI systems under increasing parametric variations and ultra-low power design for computation and communication. He has one patent and has published over 70 journal and conference papers and the book, Nana-CMOS Circuit and Physical Design. Expertise: Compact modeling for nanoscale CMOS and post-silicon technologies, Physical-level design and tools for variability and reliability, Reliable integration of emerging technologies, Low-power design solutions, high-speed interconnect and signaling techniques.


  1. Y. Cao, Predictive Technology Model for Robust Nanoelectronic Design, Springer, 2011.
  2. B. Wong, A. Mittal, Y.Cao, G. Starr, Nano-CMOS Circuit and Physical Design, John Wiley & Sons, Inc., 2004.
  3. D. Kadetotad, Z. Xu, A. Mohanty, P.-Y. Chen, B. Lin, J. Ye, S. Vrudhula, S. Yu, Y. Cao, J. Seo, "Parallel architecture with resistive cross point array for dictionary learning acceleration", IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Special Issue on Solid-State Memristive Devices and Systems, vol. 5, no. 2, pp. 194-204, 2015.
  4. Y.Cao, J. Velamala, K. Sutaria, M. S.-W. Chen, J. Ahlbin, I. S. Esqueda, M. Bajura, M. Fritze, "Cross-layer modeling and simulation of circuit reliability," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, no. 1, pp. 8-23, January 2014.
  5. J. Suh, N. Suda, C. Xu, N. Hakim, Y. Cao, B. Bakkaloglu, "Programmable analog device array (PANDA): a methodology for transistor-level analog emulation," IEEE Transactions on Circuits and Systems I, vol. 60, no. 6, pp. 1369-1380, June 2013.
  6. Z. Xu, M. Cavaliere, P. An, S. Vrudhula, Y. Cao, "The stochastic loss of spikes in Spiking Neural P systems: Design and implementation of reliable arithmetic circuits," Fundamenta Informaticae, vol. 134, no. 1-2, pp. 183-200, 2014.
  7. Z. Xu, C. Yang, M. Mao, K. Sutaria, C. Chakrabarti, Y.Cao, "Compact modeling of STT-MTJ devices," Solid-State Electronics, Elsevier Ltd., Special Issue on the 2013 European Solid-State Device Research & Circuits Conference, vol. 102, pp. 76-81, December 2014.
  8. Z. Xu, A. Mohanty, P.-Y. Chen, D. Kadetotad, B. Lin, J. Ye, S. Vrudhula, S. Yu, J. Seo, Y. Cao, "Parallel programming of resistive cross-point array for synaptic plasticity," Procedia Computer Science, Elsevier Ltd., 5th Annual International Conference on Biologically Inspired Cognitive Architectures, vol. 41, pp. 126-133, November 2014.
  9. C. Yang, Y. Emre, Z. Xu, H. Chen, Y.Cao, C. Chakrabarti, "A low cost multi-tiered approach to improving the reliability of multi-level cell PRAM," Journal of Signal Processing Systems, Elsevier Ltd., vol. 76, no. 2, pp. 133-147, August 2014.
  10. J. B. Velamala, K. B. Sutaria, H. Shimuzu, H. Awano, T. Sato, G. Wirth, Y.Cao, "Compact modeling of statistical BTI under trapping/detrapping," IEEE Transactions on Electron Devices, vol. 60, no. 11, pp. 3645-3654, November 2013.