Kaushik Roy

Kaushik Roy

Kaushik Roy is the Edward G. Tiedemann, Jr., Distinguished Professor of Electrical and Computer Engineering at Purdue University. He received his PhD from University of Illinois at Urbana-Champaign in 1990 and joined the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked for three years on FPGA architecture development and low-power circuit design. His current research focuses on cognitive algorithms, circuits and architecture for energy-efficient cognitive computing, computing models, and neuromorphic devices. Kaushik has supervised 75 PhD dissertations and his students are well placed in universities and industry. He is the co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill).

Kaushik received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, 2010 IEEE Circuits and Systems Society Technical Achievement Award (Charles Doeser Award), Distinguished Alumnus Award from Indian Institute of Technology (IIT), Kharagpur, Global foundries visiting chair at National University of Singapore, Fulbright-Nehru Distinguished Chair, DoD Vannevar Bush Faculty Fellow (2014-2019), Semiconductor Research Corporation Aristotle award in 2015.

  1. Z. Fan, P. Panda, K. Roy et. al., “Habituation based Synaptic Plasticity and Organismic Learning in Quantum Perovskite,” to appear in Nature Communications.
  2. J. Allred and K. Roy, "Unsupervised Incremental STDP Learning Using Forced Firing of Dormant or Idle Neurons," IEEE Joint International Conference on Neural Networks (IJCNN), July 2016, Vancouver, Canada.
  3. P. Panda and K. Roy, “Unsupervised Regenerative Learning of Hierarchical Features in Spiking Deep Networks for Object Recognition,” IEEE Joint International Conference on Neural Networks (IJCNN), July 2016, Vancouver, Canada.
  4. G. Srinivasan, S. Roy, V. Raghunathan, and K. Roy, “Spike Timing Dependent Plasticity Based Enhanced Self-Learning for Efficient Pattern Recognition in Spiking Neural Networks,” IEEE Joint International Conference on Neural Networks (IJCNN), May 2017.
  5. S. Sarwar, S. Venkatramani, A. Raghunathan, and K. Roy, "Multiplier-less Artificial Neurons Exploiting Error Resiliency for Energy-Efficient Neural Computing," IEEE Design, Automation and Test in Europe (DATE), March 2016.
  6. P. Panda, G. Srinivasan, and K. Roy, " EnsembleSNN: Distributed Assistive STDP learning for Energy-Efficient Conditional Inference in Spiking Neural Networks," IEEE Joint International Conference on Neural Networks (IJCNN), May 2017.
  7. P. Panda and K. Roy, “Energy Efficient and Improved Image Recognition with Conditional Deep Learning,” ACM Journal on Emerging technologies in Computing, to appear.
  8. G. Srinivasan, P. Wijesinghe, S. Sarwar, A. Jaiswal, and K. Roy, "Significance Driven Hybrid 8T-6T SRAM for Energy-Efficient Synaptic Storage in Artificial Neural Networks," IEEE Design, Automation and Test in Europe (DATE), March 2016.
  9. Sengupta, P. Panda, P. Wijesinghe, Y. Kim, and K. Roy, "Magnetic Tunnel Junction Mimics Stochastic Cortical Spiking Neurons," Nature Scientific Reports, July 2016.
  10. J. Allred and K. Roy, “Convolving over Time via Recurrent Connections for Sequential Weight Sharing in Neural Networks,” IEEE Joint International Conference on Neural Networks (IJCNN), May 2017.