Jae-sun Seo

Jae-sun Seo

Jae-sun Seo received the B.S. degree from Seoul National University in 2001, and the M.S. and Ph.D. degree from the University of Michigan in 2006 and 2010, respectively, all in electrical engineering. He spent graduate research internships at Intel circuit research lab in 2006 and Sun Microsystems VLSI research group in 2008. From January 2010 to December 2013, he was with IBM T. J. Watson Research Center, where he worked on cognitive computing chips under the DARPA SyNAPSE project and energy-efficient integrated circuits for high-performance processors. In January 2014, he joined ASU as an assistant professor in the School of ECEE. During the summer of 2015, he was a visiting faculty at Intel Circuits Research Lab. His research interests include efficient hardware design of machine learning / neuromorphic algorithms and integrated power management. Mr. Seo was a recipient of Samsung Scholarship (2004-2009), IBM Outstanding Technical Achievement Award (2012), and NSF CAREER Award (2017). He serves on the technical program committee for ISLPED (2013- ), ISOCC (2016- ), on the review committee member for ISCAS (2017), and on the organizing committee for ICCD (2015- ).

  1. Y. Ma, Y. Cao, S. Vrudhula, and J. Seo, "Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural Networks," ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), February 2017.
  2. D. Kadetotad, S. Arunachalam, C. Chakrabarti, and J. Seo, "Efficient Memory Compression in Deep Neural Networks Using Coarse-Grain Sparsification for Speech Applications," Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2016.
  3. N. Suda, G. Dasika, V. Chandra, A. Mohanty, Y. Ma, S. Vrudhula, J. Seo, and Y. Cao, "Throughput-optimized OpenCL-based FPGA accelerator for large-scale convolutional neural networks," Proceedings of ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), pp. 16-25, February 2016.
  4. J. Seo, B. Lin, M. Kim, P.-Y. Chen, D. Kadetotad, Z. Xu, Abinash Mohanty, Sarma Vrudhula, Shimeng Yu, Jieping Ye, Yu Cao, "On-chip sparse learning acceleration with CMOS and resistive synaptic devices," IEEE Transactions on Nanotechnology (TNANO), vol. 14, no. 6, pp. 969-979, November 2015.
  5. B. Rajendran, Y. Liu, J. Seo, K. Gopalakrishnan, L. Chang, D. Friedman, and M. Ritter, "Specifications of nanoscale devices and circuits for neuromorphic computational systems," IEEE Transactions on Electron Devices, vol. 60, no. 1, pp. 246-253, January 2013.
  6. M. Shah, S. Arunachalam, J. Wang, D. Blaauw, D. Sylvester, H.-S. Kim, J. Seo, and C. Chakrabarti, "A Fixed-Point Neural Network Architecture For Speech Applications on Resource Constrained Hardware," Journal of Signal Processing Systems, doi:10.1007/s11265-016-1202-x, 2016.
  7. S. Bang, J. Seo, L. Chang, D. Blaauw, and D. Sylvester, "A low ripple switched-capacitor voltage regulator using flying capacitance dithering," IEEE Journal of Solid-State Circuits (JSSC), vol. 51, no. 4, pp. 919-929, April 2016.
  8. D. Kadetotad, Z. Xu, A. Mohanty, P.-Y. Chen, B. Lin, J. Ye, S. Vrudhula, S. Yu, Y. Cao, and J. Seo, "Parallel architecture with resistive crosspoint array for dictionary learning acceleration," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 5, no. 2, pp. 194-204, June 2015.
  9. J. Seo, B. Brezzo, Y. Liu, B. Parker, S. Esser, R. Montoye, B. Rajendran, J. Tierno, L. Chang, D. Modha, and D. Friedman, "A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons," IEEE Custom Integrated Circuit Conference (CICC), pp. 1-4, September 2011.
  10. J. Seo, R. Ho, J. Lexau, M. Dayringer, D. Sylvester, and D. Blaauw, "High-bandwidth and low-energy on-chip signaling with adaptive pre-emphasis in 90nm CMOS," Proceedings of IEEE International Solid-State Circuits Conference (ISSCC), pp. 182-183, February 2010.