Arijit Raychowdhury

Arijit Raychowdhury

Arijit Raychowdhury’s research interests include low power digital and mixed-signal circuit design, design of power converters, sensors and exploring interactions of circuits with device technologies. He holds more than 25 U.S. and international patents and has published over 80 articles in journals and refereed conferences. He serves on the Technical Program Committees of DAC, ICCAD, VLSI Conference, and ISQED and has been a guest associate-editor for JETC. He has also taught many short courses and invited tutorials at multiple conferences, workshops and universities. He is the winner of the Intel Labs Technical Contribution Award, 2011; Dimitris N. Chorafas Award for outstanding doctoral research, 2007; the Best Thesis Award, College of Engineering, Purdue University, 2007; Best Paper Awards at the International Symposium on Low Power Electronic Design (ISLPED) 2012, 2006; IEEE Nanotechnology Conference, 2003; SRC Technical Excellence Award, 2005; Intel Foundation Fellowship, 2006; NASA INAC Fellowship, 2004; M.P. Birla Smarak Kosh (SOUTH POINT) Award for Higher Studies, 2002; and the Meissner Fellowship 2002. Dr. Raychowdhury is a Senior Member of the IEEE.

  1. Anvesha Amravati, Kyle Xu, Justin Romberg and A. Raychowdhury, "A 130nm 165nJ/frame Compressed-Domain Smashed-Filter Based Mixed-Signal Classifier for "In-sensor" Analytics in Smart Cameras," in IEEE Transactions on Circuits and Systems II (TCAS-II), May, 2017.
  2. Anvesha Amravati, Shaojie Xu. Ningyuan Cao, Justin Romberg and A. Raychowdhury, "A light- powered, "always on", smart camera with compressed domain gesture detection," Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), Aug., 2016.
  3. Arijit Raychowdhury, Carlos Tokunaga, Willem Beltman, Michael Deisher, James Tschanz, Vivek De, "A 2.3nJ/Frame Voice Activity Detector for Context-Aware Systems in 32nm CMOS," Journal of Solid State Circuits (JSSC), Mar. 2013.
  4. Parihar, N. Shukla, S. Datta, A. Raychowdhury, "Exploiting Synchronization Properties of Correlated Electron Devices in a Non-Boolean Computing Fabric for Template Matching," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, no.99, pp.1,10, Dec, 2014.
  5. Parihar, M. Jerry, N. Shukla, S. Datta, A. Raychowdhury, "Vertex coloring of graphs via phase dynamics of coupled oscillatory networks," Nature Scientific Reports, June 2017.
  6. Arijit Raychowdhury, Bibiche Geuskens, Keith Bowman, James Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad Khellah, Vivek De, "Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays," Journal of Solid State Circuits (JSSCC), Vol-46, Issue 4, April 2011.
  7. Bipul Paul and Arijit Raychowdhury, "Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges," in "Low-Power Variation-Tolerant Design in Nanometer Silicon", Springer Publications, USA, October 2010.
  8. Arijit Raychowdhury, Bibiche Geuskens, Jaydeep Kulkarni, Jim Tschanz, Keith Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad Khellah, "PVT & Aging Adaptive Word-Line Boosting for 8T SRAM Power reduction," Proceedings of the International Solid State Circuit Conference (ISSCC), 2010.
  9. Arijit Raychowdhury, Bibiche Geuskens, Jaydeep Kulkarni, Jim Tschanz, Keith Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad Khellah, "PVT & Aging Adaptive Word-Line Boosting for 8T SRAM Power reduction," Proceedings of the International Solid State Circuit Conference (ISSCC), 2010
  10. James Tschanz, Keith Bowman, Shih-Lien Lu, Paolo Aseron, Muhammad Khellah, Arijit Raychowdhury, Bibiche Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De, "A 45nm Resilient and Adaptive Microprocessor Core for Dynamic Variation Tolerance," Proceedings of the International Solid State Circuit Conference (ISSCC), 2010.