SoCET Subteam Brochure

Please note that the sample projects provided on each team’s entry are representative of the work done on the team, not an exhaustive list of current project work.

RTL Design

RTL design focuses on architecting, implementing, and testing different digital IP blocks and integrating them into a chip for fabrication. These projects span improvements to the RISC-V CPU core (multicore, vector processing, etc.), work on the chip interconnect, and development of digital peripherals (SPI, PWM, Timer, etc.). There is significant overlap with software for architecture development, integration testing, benchmarking, and build automation.

Skills: SystemVerilog, RISC-V assembly, C, Python, FPGA validation

Requisites: Students with ECE 270 / STARS CDP or better in digital design experience are welcome, however 337 or 437 is preferred. Projects will be assigned based on experience level.

Sample Projects:

·         QSPI FPGA Validation (270+, PCB?)

·         I2C implementation (337+)

·         AXI bus implementation (337+)

·         Optimizing 16b/8b performance in CPU vector processing (437+)

Design Flow

The process of chip design can generally be broken into two parts: the logical and the physical. Designflow is the latter, we receive RTL from digital design and produce the actual chip layout: the map of wires, transistors, IO pads, etc. that we send for fabrication. We use a variety of commercial and open-source software tools depending on the project. You will need to learn to use specific tools as the need arises.

Requisites: Experience with Linux is required. ECE 33700 ASIC Design Lab preferred.

Sample Projects:

-          Tapeout

-          Power, Performance, Area (PPA) optimization

-          SRAM Design, Power-On Reset

Software

Software projects mainly focus on developing demo applications and libraries for SoCET-designed chips, or porting existing software to our platform. Past work has included creating custom test frameworks for our chip design, porting FreeRTOS, and developing a MIDI synthesizer using AFTx07 (FPGA). Software development proceeds using both RTL simulation and FPGA versions of the current chip (a pre-silicon development environment). Pending availability of completed PCBs for past chips, there may be an opportunity to develop demos on real silicon.

For students with interest in Dev Ops, continuous integration for automating tests of our RTL is a potential project topic.

For embedded software projects, experience in 362 (or equivalent knowledge of microcontrollers) and at least one of C, C++, Rust languages preferred. For Dev Ops projects, Python experience preferred.

Skills: System languages (C, C++, Rust), RISC-V assembly, build systems, toolchains, linker script, Python

Requisites: ECE 26400 Advanced C Programming or equivalent. ECE 36200 Microprocessor System Interfacing desired but not mandatory.

Sample Projects:

·         Support multi-core in our custom test framework

·         Demo application development (focus onf new features: multi-core, vector processing)

·         Continuous Integration for RISC-V core

·         Improved bootloader

Analog/Mixed Signal (AMS)

AMS Circuit Projects focuses on the development and integration of circuits that process both analog and digital signals within a single system. Analog circuits deal with continuous signals, like sound or radio waves, while digital circuits handle discrete signals, represented by binary data. The key challenge in AMS design is to achieve high performance and precision in environments where both types of signals coexist, often leading to complex interactions between analog and digital components.

Requisites: Experience on Analog/Mixed signal or RF circuits and system design in CMOS technology is required. ECE 455/456 (or Cadence in general) is highly recommended. Must be a returning student to be taken as a senior design student.

GPU Architecture

The GPU team focuses on studying and optimizing SIMT architectures. We have developed a novel SIMT scalar architecture, and will work on optimizing this architecture and conducting workload analysis to find and optimize interesting patterns. We work with GPU Architecture, RTL, and Cycle Accurate Simulators.

Requisites: Completion of 337 is required; 437 concurrent is preferred.

Polymorphic Logic

This team is focused on a new platform of design specific to protecting design IP from piracy and reverse engineering. This is accomplished at the device level with new types of devices and macro level layouts. To be a proficient member you will need to be versed in many of the same skills as digital design as well as verification. In addition to being knowledgeable about digital design, it would also be helpful to have some basic programming skills to assist in testing new research tools against our design ideas as well designing our own tools for using this platform.

Requisites: Students with ECE 270 / STARS CDP or better in digital design experience are welcome, however 337 is preferred.

Magnetic Random Access Memory (MRAM)

Like SRAM and DRAM, MRAM is a type of memory that can serve as a small repository close to your SoC. Unlike most SRAM and DRAM, MRAM is a non-volatile form a memory which means its does not require constant power for operation. This makes it a great resource for low-powered energy platforms and designs; however, it can have other drawbacks that need to be explored. The goal of this team is to explore those drawbacks and come up with designs to better improve the reliability and sustainability of MRAM. We will work with FPGAs and digital design skills are necessary to be a proficient member as well as basic understanding of programming to design graphics and do data analysis.

Requisites: Students with ECE 270 / STARS CDP or better in digital design experience are welcome, however 337 is preferred for digital design work. Coursework in C and/or Python programming.

AI Hardware

Designing a matrix multiplication accelerator and accompanying software stack.

·         Develop AI accelerator for both training and inference

·         Full software–hardware stack: PyTorch kernels, system software, compiler, architecture, and RTL

·         Focus on performance, efficiency, and scalability through hardware–software co-design

·         Split into: system software, compilers, vector core, scheduler, systolic array, scratchpad, and DRAM/memory

Requisites: ECE 437 (Hardware), ECE 468/573 (Compiler/PyTorch). Experience in AI (PyTorch, training) is recommended but not required.

UVM Verification

SoC designs in industry require extremely thorough functional verification on designs several orders of magnitude larger than anything one does in coursework or even in SoCET. The test benching techniques you learn in ECE 33700 are suited to the complexity of designs done in ECE 33700, but the coding style does not scale well to much larger designs and much more extensive functional verification. The most widely used approach to industry scale functional verification is UVM (Universal Verification Methodology). Most of the industry uses either UVM or a similar process that was defined before UVM was available as a standard. In the SoCET UVM Verification subteam, you will first learn and practice UVM techniques, learn to prepare a test plan, and then apply it to portions of SoCET’s current SoC design.

Requisites: Completion of 337 is required

PCB and Bring-Up Team

The PCB/Bring-Up team focuses on designing, developing, and manufacturing printed circuit boards that serve as test platforms for SoCET's taped-out System-on-Chips (SoCs). Our work bridges the gap between silicon and real-world applications by creating reliable testing environments for AFT-X0n series and other SoC projects. The team handles the complete PCB development cycle, from initial schematic capture through layout and assembly, ensuring proper power delivery, signal integrity, and peripheral integration for chip validation.

Skills: KiCAD, Schematic Design, Circuit Design, PCB Layout Techniques, Soldering, Hardware Debugging.

Recommended Courses: ECE 20007, ECE 20008, ECE 20001, ECE 36200, ECE 30411

Data Center Network

Develop a network accelerator for datacenter and distributed systems workloads and demonstrate on an FPGA prototype.

·         Full-stack design: networking stack, software, architecture, and RTL

·         Focus on high throughput, low latency, and scalable data movement

Requisites: Completion of ECE 33700