Annual Workshop on Chips and AI

Tuesday, September 22, 2026
(Registration Required)
Purdue Material Sciences and Electrical Engineering Building
501 Northwestern Avenue
West Lafayette, IN 47907

Past Events

Workshop on CHIPS and AI, October 17, 2025
Institute Kickoff Event, November 19, 2024

Workshop on Chips and AI, September 22, 2026

This event serves as the next annual workshop of the Institute of Chips and AI, building on the momentum established at the Institute?s kickoff workshop in November 2024 and the successful 2025 workshop. As a gathering point for returning and new participants, the workshop provides an opportunity to reconnect, share progress, strengthen collaborations, and identify new directions for research and innovation. This year's event will expand participation through broader registration opportunities and will introduce a hackathon designed to foster hands-on engagement, creativity, and interdisciplinary collaboration.

The Workshop on Chips and AI, sponsored by the U.S. National Science Foundation FuSe-TG: FAB: A Heterogeneous Ferroelectronics Platform for Accelerating Big Data Analytics and the Institute of Chips and AI, will bring together distinguished industry leaders, researchers, and Purdue University students to discuss the latest advances and challenges in topics including Hardware Technologies for Neural Computing, Systems and Architectures for Next Generation AI, and AI for Chip Design. Participants will have the opportunity to connect with emerging talent, explore cutting-edge research, and engage in meaningful conversations that foster collaboration, innovation, and the continued growth of the Institute's research community.

The workshop is organized by a dedicated committee of Purdue students who are actively involved in the Institute's efforts to advance AI research and innovation and are passionate about strengthening Purdue University's leadership in the rapidly evolving global AI and semiconductor landscape. Through this event, the committee aims to cultivate connections across academia, industry, and government while creating opportunities for students to contribute to the development of next-generation AI technologies, support the Institute's mission of moving AI forward, and expand their real-world impact.

Join the Hackathon!

Agenda

Tuesday, September 22, 2026
Time	Location	Topic	Speaker(s)/Participant(s)
8:30-9:00 a.m.	Rice Design Studio (MSEE 190)	Registration and Breakfast	All Participants
9:00-9:40 am	Rice Design Studio (MSEE 190)	Welcome/Opening Ceremony	Milind Kulkarni, Purdue
		Institute Overview	Kaushik Roy, Purdue

9:40-10:00 a.m.	Rice Design Studio (MSEE 190)	Plenary Talk: TBD	Sang Phill Park Principle Engineer, Oracle
10:00-10:20 a.m.	Rice Design Studio (MSEE 190)	Plenary Talk: TBD	Swagath Venkataramani Principal Research Scientist, IBM T.J Watson Research Center
10:20 a.m. - 10:40 a.m.	Rice Design Studio (MSEE 190)	Plenary Talk: TBD	Charles Augustine Circuit Design Engineer, NVIDIA Inc.
10:40-11:40 a.m.	Rice Design Studio (MSEE 190)	Panel - The Future of AI Computing: Workloads, Architectures, and Systems	Moderator: TBD Charles Augustine Circuit Design Engineer, NVIDIA Inc. Sang Phill Park Principle Engineer, Oracle Swagath Venkataramani Principal Research Scientist, IBM T.J Watson Research Center
Break: 11:40 a.m. - 11:50 a.m.
11:50 a.m.-12:50 p.m.	Rice Design Studio (MSEE 190)	Student Lightning Talks
Lunch: 12:50 - 1:15 p.m.
1:15-2:45 p.m.	Rice Design Studio (MSEE 190)	Poster Session & Hackathon Demos	Student Poster List Student Poster Presenters
2:45-3:05 p.m.	Rice Design Studio (MSEE 190)	Plenary Talk: TBD	Siri Narla Embedded NVM Technology Architect, Global Foundries
3:05-3:25 p.m.	Rice Design Studio (MSEE 190)	Plenary Talk: TBD	TBD
3:25-3:40 p.m.	Rice Design Studio (MSEE 190)	Results and Awards
3:40-4:40 p.m.	Rice Design Studio (MSEE 190)	Panel - AI-Native Chip Design: From Data-Driven EDA to Trustworthy Design Automation	Moderator: TBD Kunhyuk Kang Lead Corporate Vice President, Samsung Siri Narla Embedded NVM Technology Architect, Global Foundries Sandeep Thirumala Senior Engineer - Advanced DRAM Process Integration, Micron Technology Srividhya Venkataraman Fellow Silicon Design Engineer, AMD
4:40-5:00 p.m.	Rice Design Studio (MSEE 190)	Industry Panel - Career Advice
5:00 p.m.	Rice Design Studio (MSEE 190)	Closing + Networking Session

Student Posters

Tuesday, September 22, 2026
Number	Authors	Title	Abstract/Bio
1	M. Mukherjee, K. Roy	MIRAGE:MRAM-Based Near ADC-Less Compute-In-Memory Macro for Deep Learning Acceleration
2	S. Bose, K. Roy	Partial Sum Quantization for Near ADC-Less CiM Accelerators
3	A. Kosta, K. Roy	Fault-Adaptive CPG Locomotion: Gait Emergence and Cost of Transport Under Joint Seizure and Actuator Degradation
4	A. Pranta, K. Roy	To CiM or Not to CiM
5	D. Lee, K. Roy	ViP-VLA: Vision-Internal Token Pruning for Efficient Vision-Language-Action Models
6	A. Joshi, K. Roy	SHIRE: Enhancing Sample Efficiency using Human Intuition in REinforcement Learning
7	R. Koduru, K. Roy	Integrating BEOL IGZO eDRAM as On-die Scratchpad for GPUs via System Technology Co-optimization
8	A. Mukherjee, K. Roy	DRC-Aid: Design-Rule Violation Correction via Agentic Framework utilizing Inference-Time Large Language Models
9	G. Yarramneni, A. Raghunathan	Agentic Design Space Exploration for Joint Hardware Configuration Selection and Mapping of AI Inference Workloads on Heterogeneous Edge SoCs
10	J. Balasubramanian, A. Raghunathan	PowerScope: ML-based Intra-Cycle Power Estimation Abstract Power estimation at sub-clock-cycle temporal resolutions is critical for tasks such as power delivery network (PDN) design, dynamic voltage droop analysis, and pre-silicon power side-channel security evaluation. Designers commonly rely on commercial post-layout gate-level power analysis tools for these tasks, but these flows are computationally expensive and scale poorly with design size and workload length. Machine learning (ML)-based power estimation frameworks have shown promise in accelerating power estimation, but prior efforts only address average power or per-cycle power estimation. We propose PowerScope, the first ML-based intra-cycle power estimation framework. PowerScope operates purely on RTL simulation traces at inference time, eliminating the need for post-layout gate-level simulation and power analysis per workload. Across a diverse benchmark suite, PowerScope achieves 3.3% median and 6.7% mean absolute percentage error compared to commercial post-layout gate-level power estimates while running ∼571� faster. We further demonstrate that PowerScope's predictions can be reliably used for the downstream task of pre-silicon power side-channel leakage assessment.
11	I. Ahmed, S. Gupta	1.58-b FeFET-Based Ternary Neural Networks: Achieving Robust Compute-In-Memory With Weight-Input Transformations
12	S. Bhattacharjee, S. Gupta	WEBCRAFT: Weight Transformations in Bit-Sliced Crossbar Arrays for Fault Tolerant Computing-in-Memory: Design Techniques and Evaluation Framework
13	D. Kim, S. Gupta	SCION: A Comprehensive Simulation Framework for Charge-Based In-Memory Computing for Rapid Evaluation of Hardware Non-Idealities and DNN Accuracy
14	A. Das, V. Raghunathan	COSMOS: Designing Energy-Efficient Context-Aware Multimodal Cognitive Systems
15	H. Kim, V. Raghunathan	TESSERA: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs
16	E. Berscheid, A. Raghunathan	Optimizing Data Placement for Near-Memory Acceleration of Recommendation Systems Abstract Recommendation systems are widely-used machine learning models that process user data to recommend content. These models heavily rely on looking up and summing embedding vectors from large tables, which is a memory-bound operation that bottlenecks performance. Near-memory processing (NMP) accelerates embedding look- ups by employing processing units within the DRAM system, which compute multiple vector operations in parallel and reduce data volume before transferring the results to the host. We observe that data placement has a profound impact on NMP efficiency, an effect that is not fully addressed by prior work. To that end, we make the following contributions: First, we propose a memory-efficient statistical method for profiling embedding table look-ups to find commonly co-occurring sets of vectors. We recognize that vector replication holds potential for enhancing vector co-locality, and not only load balance as explored in prior works. Accordingly, our second contribution is a replicate resolution policy that enables a principled and tunable trade-off between load balance and vector co-locality to maximize performance. Next, we redistribute non-replicated embedding vectors in physical DRAM to collocate (or separate) vectors that are likely (or unlikely) to belong to the same access set. DRAM simulations demonstrate up to 3.41x speedup and 3.01x energy savings over prior methods. Bio Elijah Berscheid is a PhD student in ECE, advised by Professor Anand Raghunathan. His research interests relate to efficient data center scale AI, including systems, architecture, and algorithms. His previous project aimed to optimize near-DRAM computing performance for memory-bound recommendation system workloads (under review at TCASAI). His current work explores performance gaps due to dynamic irregularities in sparse decode attention for long-context workloads to improve performance on chiplet-based accelerators. Elijah has interned at the University of Minnesota (control systems and data processing), Western Digital (HDD servo firmware), Broadcom (3nm ROM verification), and NVIDIA (efficient LLM inference on future MCM-GPUs).
17	M. Chen, H. Li	Cross-Layer Heterogeneous Memory Systems for Scalable AI and Optimization Workloads Abstract Emerging AI and optimization workloads place increasing pressure on the memory hierarchy through growing capacity, bandwidth, and data- movement demands. At the same time, emerging memory technologies provide new opportunities to redesign how data is stored, moved, and processed across the hierarchy. This work explores cross-layer heterogeneous memory architectures that match the characteristics of different memory technologies with workload requirements. We investigate eDRAM?RRAM heterogeneous memories for hyperdimensional computing and zeroth-order fine-tuning, stochastic MTJ compute-in- memory for Ising optimization, and HBM?HBF systems for large language model inference. Across these systems, we study how device and circuit characteristics translate into architectural tradeoffs in data placement, computation, bandwidth utilization, and energy efficiency. Together, these efforts establish a cross-layer methodology for building scalable memory hierarchies for emerging AI and optimization workloads. Bio Mufeng Chen received the B.S. degree in optics and electronic information engineering from Huazhong University of Science and Technology, Wuhan, China, in 2021. From 2021 to 2024, he was a Research Assistant with Zhejiang University, Hangzhou, China, where he worked on hardware/software co-design and system integration for emerging computing systems. He is currently pursuing the Ph.D. degree with the Elmore Family School of Electrical and Computer Engineering, Purdue University, West Lafayette, USA. His research interests include heterogeneous memory systems, memory-centric architectures, hardware/software co-design, and system-level integration for data- intensive computing.
18	S. Chandra, K. Roy	2D-ThermAl: TCAD Model Informed Thermal Analysis of Circuits using GenAI Abstract Thermal analysis is increasingly critical in modern integrated circuits, where non-uniform power dissipation and high transistor densities can cause rapid temperature spikes and reliability concerns. Traditional methods such as FEM-based simulations offer high accuracy but computationally prohibitive for early-stage design, often requiring multiple iterative redesign cycles to resolve late-stage thermal failures. To address these challenges, we propose '2D-ThermAl', a physics-informed generative AI framework which effectively identifies heat sources and estimates full-chip transient and steady-state thermal distributions directly from input activity profiles. ThermAl employs a hybrid U-Net architecture enhanced with positional encoding and a Boltzmann regularizer to maintain physical fidelity. Our model is trained on an extensive dataset of heat dissipation maps for more than 200 circuit configurations, ranging from simple logic gates (e.g., inverters, NAND, XOR) to complex designs, generated via COMSOL and Cadence EDA flows. The dataset captures diverse activity patterns, and we note that material-dependent thermal properties may require targeted fine-tuning to ensure accuracy across different fabrication contexts. Experimental results demonstrate that ThermAl delivers precise temperature mappings for large circuits, with a root mean squared error (RMSE) of only 0.71�C and outperforms conventional FEM tools by running up to ~200x faster. We analyze performance across diverse layouts and workloads and discuss its applicability to large-scale EDA workflows. While thermal reliability assessments often extend beyond 85�C for post-layout signoff, our focus here is on early-stage hotspot detection and thermal pattern learning. To ensure generalization beyond the nominal operating range (25-55�C), we additionally performed cross-validation on an extended dataset spanning 25-95�C maintaining a high accuracy (<2.2% full-scale RMSE) even under elevated temperature conditions representative of peak power and stress scenarios.} Limitations such as 2D-only modeling and real-world validation are addressed with concrete future directions, including 3D extension, generalization across technology nodes, and transfer learning strategies. Bio Soumyadeep Chandra received his B.Tech degree in Electrical and Telecommunication Engineering from Jadavpur University, Kolkata, India in 2020. Currently, he is a 6th year Ph.D. student in the School of Electrical and Computer Engineering at Purdue University, West Lafayette, IN, under the mentorship of Prof. Kaushik Roy. His ongoing research focuses on areas such as procedural learning, scene understanding, surgical workflow analysis, and generative AI for hardware.

Accomodations

The Union Club Hotel at Purdue University - Website
Hilton Garden Inn West Lafayette Wabash Landing - Website
Hampton Inn & Suites West Lafayette - Website

Contact Us

For questions, please email CHIPSandAI@purdue.edu.