- Committee Member, VLSI Technology and Circuits, IEEE Electron Device Society (EDS)
- TPC Member, Design Automation Conference (DAC), 2023
- Review Editor, Frontiers in Neuroscience
- Proceedings of the IEEE
- IEEE Electron Device Letters (EDL)
- IEEE Trans. Electron Devices (TED)
- IEEE Journal of Solid-State Circuits (JSSC)
- IEEE Transactions on Computers
- IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
- IEEE Trans. Nanotechnology (T-NANO)
- IEEE Trans. VLSI (T-VLSI)
- IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (T-CAD)
- IEEE Transactions on Biomedical Circuits and Systems (TBioCAS)
- Scientific Reports
- Frontiers in Neuroscience
- Applied Physics Letters (APL)
- Nanoscale Research Letters (NRL)
- Journal of the Electron Devices Society (J-EDS)
- Journal of Physics D: Applied Physics (JPhys-D)
Invited Talks and Tutorials
H. Li, “Nanotechnology-Inspired AI Hardware for Learning and Inference,” ICCAD Workshop on Hardware and Algorithms for Learning On-a-chip (HALO), Nov. 2022.
H. Li and H.-S. P. Wong, “3D MOSAIC with N3XT Chips,” The Global Projects Center, Stanford, CA, Aug. 2022.
H. Li, “RRAM-CMOS integrated hardware for efficient learning and inference at the edge,” IEEE EDS Workshop on Memory Based Applications, Jan. 2022.
H. Li, “RRAM-CMOS integrated hardware for efficient learning and inference at the edge,” Guest Lecture in ‘ELEC 515: Embedded Machine Learning’, Rice University, Nov. 2021.
H. Li, W. Wan, and H.-S. P. Wong, “In- and near-memory computing using 2D/3D resistive memories,” Tutorial, IEEE Electron Devices Technology and Manufacturing (EDTM), March 2021.
H. Li, W. Wan, and H.-S. P. Wong, “In- and near-memory computing using 2D/3D resistive memories,” Tutorial, IEEE Semiconductor Interface Specialists Conference (SISC), Dec. 2020.
H. Li and S. Mitra, “NanoSystems for Edge Intelligence,” Stanford Wearable Electronics (eWEAR) Symposium, Stanford, CA, Sep. 2019.
H. Li, “ET meets AI: emerging memory technologies for efficient on-device machine learning,” Seminar at UC Davis, Davis, CA, Aug. 2019
H. Li, P. Raina, and H.-S. P. Wong, “Neuro-inspired computing with emerging memories: where device physics meets learning algorithms,” SPIE Spintronics Symp., San Diego, CA, Aug. 2019.
H. Li, “Towards efficient machine learning hardware with emerging memories,” Invited Talk at Arm Ltd., San Jose, CA, May 2019.
H. Li and H.-S. P. Wong, “Device-to-system modeling of RRAM for NVM-centric architectures,” NCCAVS Advanced Memory Workshop, Milpitas, CA, Dec. 2018.
H. Li, “In-memory computing with 3D vertical RRAM (VRRAM),” Seminar at University of Texas at Austin, Austin, TX, Aug. 2018.
H. Li and H.-S. P. Wong, “3D vertical resistive RAM (VRRAM) for in-memory computing,” IEEE/ACM Workshop on Variability, Modeling, and Characterization (VMC), Irvine, CA, Nov. 2017.
H. Li, T. Wu, S. Mitra, and H.-S. P. Wong, “Device-architecture co-design for hyperdimensional computing with 3D vertical resistive switching random access memory (3D VRRAM),” VLSI-TSA (Technology Highlights Session), Hsinchu, Taiwan, April 2017.
H. Li and H.-S. P. Wong, “Resistive RAM-centric computing: Design and modeling methodology,” Emerging Memory Solutions Workshop, 2017 DATE, Lausanne, Switzerland, March 2017.
H. Li and H.-S. P. Wong, “Brain-inspired in-memory computing with 3D vertical RRAM,” IEEE-CEDA Design Automation Futures Workshop, Fremont, CA, Oct. 2016.
H. Li, “Device-architecture co-design for brain-inspired in-memory computing,” Seminar at Tsinghua University, Beijing, China, Dec. 2016.