As device shrinks, novel concept devices and/or better materials than Si are required. The integration of III-V is mainly driven by the high electron mobility of these materials. Also, Tri-gate structure is the most favourable architecture for Lg scaling due to SCE degradation. We combined all these benefits to compare the properties of III-V (InGaAs) and Si MOSFET / FinFETs at short gate length. Here we demonstrate where this technology is a viable alternative to Si in the next successive node of the ITRS.
- Performance Comparisons of III-V and Strained-Si planar FETs and FinFETs at Lg=12nm
- Use real-space effective mass approximation for 2-D and 3-D structures.
- m* extracted from full-bands.
- Data analysis: VINJ, NINV, and extracted SS, DIBL, and ON-current from I-V characteristics.
- Include Series Resistance (RS/D).
- Integrate high-k gate dielectrics (HfO2).
- Impact of channel material property and device architecture.
- InGaAs does not outperform Si in the ballistic transport regime: DOS BOTTLENECK
- Multi-gate structures suppress the short channel effects very well.
- Contact resistance dominates the overall device performance.
- IEEE TED 2012 Vol. 59, No. 8.
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