Journals (7)
"Optimum High-k Oxide for the Best Performance of Ultra-scaled Double-Gate MOSFETs"
IEEE Transactions on Nanotechnology (2016);doi:10.1109/TNANO.2016.25834112016Not Cited Yet
0
0
"Design Guidelines for Sub-12 nm Nanowire MOSFETs"
IEEE Transactions on Nanotechnology, vol. 14, Issue: 2, Page(s): 210 - 213, March 2015;doi: 10.1109/TNANO.2015.239544120150
15
"Transistor roadmap projection using predictive full-band atomistic modeling"
Appl. Phys. Lett. 105, 083508 , published online 28 August 2014;doi:10.1063/1.489421720140
7
"Performance Comparisons of III-V and strained-Si in Planar FETs and Non-planar FinFETs at Ultra-short Gate Length (12nm)"
IEEE Transactions on Electron Devices, vol. 59, Issue: 8, Page(s): 2107 - 2114, Aug. 2012;doi:10.1109/TED.2012.21984812012Not Cited Yet
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0
"Calculation of Phonon Spectrum and Thermal Properties in Suspended <100> InXGa1-XAs Nanowires"
Journal of Computational Electronics March 2012, Volume 11, Issue 1, pp 22-28;doi:10.1007/s10825-012-0389-82012Not Cited Yet
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0
"Enhanced valence force field model for the lattice properties of gallium arsenide"
Physical Review B, Vol. 84, pg. 155204, Published 17 October 2011;doi :10.1103/PhysRevB.84.1552042011Cited by 8 / 17 Downloads
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8
"Strain-induced, off-diagonal, same-atom parameters in empirical tight-binding theory suitable for [110] uniaxial strain applied to a silicon parameterization"
Phys. Rev. B, Vol 81, 125202 (2010);doi:10.1103/PhysRevB.81.1252022010Cited by 1 / 118 Downloads
118
1
Proceedings (8)
"Tunneling: The Major Issue in Ultra-scaled MOSFETs"
IEEE Nano, Rome, Italy, July 26-30, 2015, Pages: 670 - 673;doi:10.1109/NANO.2015.73886942015Not Cited Yet
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"More Moore landscape for system readiness-ITRS2. 0 requirements"
32nd IEEE International Conference on Computer Design (ICCD), pp. 147-152, Oct. 2014;doi: 10.1109/ICCD.2014.69746742015Not Cited Yet
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0
"Atomistic simulation of steep subthreshold slope Bi-layer MoS2 transistors"
2014 IEEE Silicon Nanoelectronics Workshop (SNW), 8-9 June 2014, Honolulu, HI, Page(s): 1 - 2;doi:10.1109/SNW.2014.73486062014Not Cited Yet
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"Performance degradation due to thicker physical layer of high k oxide in ultra-scaled MOSFETs and mitigation through electrostatics design"
2014 IEEE Silicon Nanoelectronics Workshop (SNW), 8-9 June 2014, Honolulu, HI, Page(s): 1 - 2;doi:10.1109/SNW.2014.73485672014Not Cited Yet
0
0
"Quantum Corrected Drift-Diffusion Simulation for Prediction of CMOS Scaling"
Device Research Conference, 20132013Not Cited Yet
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0
"Parameter Fitting for Lattice Properties of Gallium Arsenide using Parallel Genetic Algorithm"
2011 IEEE Congress on Evolutionary Computation, 5-8 June 2011;doi:10.1109/CEC.2011.59499182011Not Cited Yet
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"Single Layer MoS2 Band Structure and Transport"
International Semiconductor Device Research Symposium (ISDRS 2011), Dec 7-11, Univ of Maryland2011Not Cited Yet
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"Contact Modeling and Analysis of InAs HEMT Transistors"
IEEE proceedings of IEEE Nanotechnology Materials and Devices Conference (IEEE NMDC 2011), Oct. 18-21, 2011 at The Shilla Jeju, Korea2011Cited by 1 / 26 Downloads
26
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Conferences (19)
"Tunneling: The Major Issue in Ultra-scaled MOSFETs"
IEEE Nano, Rome, Italy, July 26-30, 201520150
0
"Development of the NEMO Tool Suite From Basic Physics to Real Devices and to Global Impact on nanoHUB.org"
Arizona State, Electrical Engineering Advanced Semiconductor Device Class, Host: Prof. Dragica Vasileska, April 20, 201520150
0
"Transport Properties of 2D Material Transistors"
TECHON 2014, October 1-3, 2014, Santa Clara, CA20140
0
"Atomistic Simulation of Steep Subthreshold Slope Bi-layer MoS2 Transistors"
Poster Session, 2014 IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI USA June 8-9, 201420140
0
"Performance Degradation due to Thick Physical Layer of High-k Oxide in Ultra- scaled MOSFETs and Mitigation through Electrostatics Design"
2014 IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI USA June 8-9, 201420140
0
"Development of the NEMO Tool Suite From Basic Physics to Real Devices and to Global Impact on nanoHUB.org"
Embedded tutorial on FinFET: A Multifaceted Perspective for CAD Engineers , International Conference on Computer Aided Design, Nov 18-21, 2013, San Jose, CA20130
0
"Quantum Mechanical Modifications of Drift-diffusion Simulators for Ultra-scaled MOSFETs"
TECHCON, 201320130
0
"On the Scaling Issues and Possible Solutions for Double Gate MOSFETs at the End of ITRS"
accepted for TECHCON 201320130
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"PMOS FinFETs Enhanced through Transport in SiGe Cladding"
submitted to IEDM2013.20130
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"On the Scaling Issues and Solutions for Double Gate MOSFETs at the end of ITRS Roadmap"
accepted for ISDRS 201320130
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"Performance Comparison of InGaAs and strained-Si in Planar and Non-planar FETs at Ultra-short Gate Length (12nm)"
20120
0
"Phonon Spectrum and Thermal Properties of free standing <100> and <111> InGaAs alloy nanowires"
APS March Meeting 2012, Boston, US20120
0
"Contact-to-channel Resistance Modeling in HEMT Devices"
MSD review May 2012, Boston. 20120
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"Exploring the Impact of nanoHUB.org on Research and Education"
HUBbub 2011, the HUBzero conference, April 5-6, 2011, Indianapolis. Presentation online at http://hubzero.org/resources/42920110
0
"Parameter Fitting for Lattice Properties of Gallium Arsenide using Parallel Genetic Algorithm"
2011 IEEE Congress on Evolutionary Computation, 5-8 June 2011;doi:10.1109/CEC.2011.594991820110
0
"Model development for lattice properties of gallium arsenide using parallel genetic algorithm "
Evolutionary Computation (CEC), 2011 IEEE Congress on, Page(s): 2429 - 2435; doi: 10.1109/CEC.2011.594991820110
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"Contact Modeling and Analysis of InAs HEMT Transistors"
IEEE proceedings of IEEE Nanotechnology Materials and Devices Conference (IEEE NMDC 2011), Oct. 18-21, 2011 at The Shilla Jeju, Korea20110
0
"Single Layer MoS2 Band Structure and Transport"
2011 International Semiconductor Device Research Symposium (ISDRS 2011), Dec 7-11, Univ of Maryland20110
0
"Contact Modeling in HEMT Devices"
MSD/ FCRP Annual Review, Student Poster, MIT, Boston, MA, May 10-11, 2011.20110
0