Journals (6)
"Switching Mechanism and the Scalability of vertical-TFETs"
, 2018, Vol. 65, No. 7, Pages 3065-30682018Not Cited Yet
0
0
"Dramatic Impact of Dimensionality on the Electrostatics of P-N Junctions and Its Sensing and Switching Applications"
IEEE Transactions on Nanotechnology, 2018, Vol. 17, No. 2, Pages 293-2982018Not Cited Yet
0
0
"Transport in vertically stacked hetero-structures from 2D materials"
IOP Journal of Physics: Conf. Series 864 (2017) 012053;doi:10.1088/1742-6596/864/1/0120532017Not Cited Yet
0
0
"Thickness Engineered Tunnel Field-Effect Transistors based on Phosphorene"
IEEE Electron Device Letters, Volume: 38, Issue: 1, Jan. 2017, Pages: 130 - 133;doi: 10.1109/LED.2016.26275382016Not Cited Yet
0
0
"Configurable Electrostatically Doped High Performance Bilayer Graphene Tunnel FET"
IEEE Journal of the Electron Devices Society, Volume:4 ,Issue: 3, Page(s): 124 - 128, May 2016;doi:10.1109/JEDS.2016.25399192015Not Cited Yet
0
0
"In-surface confinement of topological insulator nanowire surface states"
Appl. Phys. Lett., vol. 107, no. 12, pp. 121605, Sep. 2015;doi:10.1063/1.493197520150
2
Proceedings (5)
"III-N heterostructure devices for low-power logic"
Proceedings of the Semiconductor Technology International Conference (CSTIC), 2017 China, Pages 1-3;doi:10.1109/CSTIC.2017.79197432017Not Cited Yet
0
0
"Transport in vertically stacked hetero-structures from 2D materials"
33rd International Conference on the Physics of Semiconductors, Beijing, China on July 31- August 5, 2016 2016Not Cited Yet
0
0
"Electrically Doped 2D matertial tunnel transistor"
International Workshop on Computational Electronics (IWCE 2015) September 2, 2015 West Lafayette, Indiana USA, Pages: 1 - 3;doi:10.1109/IWCE.2015.73019662015Not Cited Yet
0
0
"NEMO5: Why must we treat topological insulator nanowires atomically?"
IWCE, September 2, 2015 West Lafayette, Indiana USA2015Not Cited Yet
0
0
"Achieving a higher performance in bilayer graphene FET - strain engineering"
the 20th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Washington DC, 9-11 Sep. 2015, Pages: 177 - 181;doi:10.1109/SISPAD.2015.72922882015Not Cited Yet
0
0
Conferences (12)
"III-N heterostructure devices for low-power logic"
2017 China Semiconductor Technology International Conference (CSTIC), Shanghai, China, March 12-13, 2017 20170
0
"Why Do We Need Novel Steep Transistors?"
TECH CON 2016, Sept. 11 - Tuesday, Sept. 13, 2016, Renaissance Austin Hotel, Austin, TX, United States20160
0
"Transport in vertically stacked hetero-structures from 2D materials"
33rd International Conference on the Physics of Semiconductors, Beijing, China on July 31- August 5, 2016 20160
0
"Atomistic Modeling of Interlayer TFETs"
2016 LEAST review, August 10 & 11, 2016, University of Notre Dame20160
0
"Atomistic Modeling of WTe-MoS2 Interlayer TFETs"
TECH CON 2016, Sept. 11 - Tuesday, Sept. 13, 2016, Renaissance Austin Hotel, Austin, TX, United States20160
0
"Atomistic modeling of 2D material devices"
US-EU workshop on 2D layered materials and devices, Arlington, Virginia, April 22, 201520160
0
"STEEP Transistor Modeling with NEMO5"
Steep Transistors Workshop, University of Notre Dame, Notre Dame, IN, October 5-6, 201520150
0
"Transport properties of bilayer graphene field effect transistor"
TECHCON 2015, Sept. 20-22, 2015, Austin, TX, United States20150
0
"Electrically Doped 2D Material Tunnel Transistors"
International Workshop on Computational Electronics (IWCE 2015) September 2, 2015 West Lafayette, Indiana USA20150
0
"NEMO5: Why must we treat topological insulator nanowires atomically?"
International Workshop on Computational Electronics (IWCE 2015) September 2, 2015 West Lafayette, Indiana USA20150
0
"Achieving a higher ON/OFF ratio in Bilayer Graphene FET-- Strain Engineering"
The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Washington DC, USA, September 9-11, 201520150
0
"High Performance Bilayer graphene transistors"
LEAST review, student poster, South Bend, IN, Aug. 201520150
0