Wide Bandgap Devices Group

M. Sampath, D. T. Morisette, J. A. Cooper, “Constant-Gate-Charge Scaling for Increased Short-Circuit Withstand Time in SiC Power Devices,” 2020 IEEE International Reliability Physics Symposium (IRPS), May 2020. [LINK]

I. Jayawardhena, T. Isaacs-Smith, A. C. Ahyi, R. P. Ramamurthy, K. Ramadoss, D. Morisette, S. Dhar, “Electrical Characterization of 4H-SiC/ALD-Al2O3 Interface for Different Surface Preparations,” presented at the 2020 Electronic Materials Conference, June 24-26, 2020. [LINK]

I. Jayawardhena, A. Ahyi, T. Isaacs-Smith, R. Ramamurthy, D. Morisette, S. Dhar, “Trap Characterization of ALD Al2O3/4H-SiC Metal-Oxide-Semiconductor Interfaces,” 2019 ECS Meeting Abstracts, Vol. MA2019-02 887. [LINK]

J. A. Cooper, D. T. Morisette, M. Sampath, “Increased Short-Circuit Withstand Time and Reduced DIBL by Constant-Gate-Charge Scaling in SiC Power MOSFETs,” poster presented at the 2019 International Conference on Silicon Carbide and Related Materials, September 29 – October 4, 2019.

M. Sampath, J. A. Cooper, A. Salemi, D. T. Morisette, “The IMOSFET: A Deeply-Scaled, Fully-Self-Aligned Trench MOSFET,” poster presented at the 2019 International Conference on Silicon Carbide and Related Materials, September 29 – October 4, 2019.

I. U. Jayawardhena, A. C. Ahyi, T. Isaacs-Smith, R. Ramamurthy, K. Ramadoss, C. Jiao, D. Morisette, R. Thorpe, L. C. Feldman, S. Dhar, “Al2O3 / 4H-SiC MOS interface characterization with different surface treatments,” poster presented at the 2019 International Conference on Silicon Carbide and Related Materials, September 29 – October 4, 2019.

N. Opondo, J. A. Cooper, H. Liao, W. Chen, D. T. Morisette, “The Waffle Substrate: A Novel Approach to Reducing Substrate Resistance in SiC Power Devices,” poster presented at the 2019 International Conference on Silicon Carbide and Related Materials, September 29 – October 4, 2019.

P. L. Yu, N. Opondo, S. Dai, B. Jiang, D. T. Morisette, S. A. Bhave, “Single Crystalline 4H-SiC Membrane Resonators,” 2018 IEEE International Frequency Control Symposium (IFCS) Proceedings, p. 5, 2018

Md. M. Alam, D. T. Morisette, J. A. Cooper, “Practical Design of 4H-SiC Superjunction Devices in the Presence of Charge Imbalance,” Materials Science Forum, Vol. 924, pp. 563-567, 2018.

J. A. Cooper, N. Islam, R. P. Ramamurthy, D. T. Morisette, “Vertical Tri-Gate Power MOSFETs in 4H-SiC,” Materials Science Forum, Vol. 924, pp. 680-683, 2018.

M. Sampath, D. T. Morisette, J. A. Cooper, “Comparison of Single- and Double-Trench UMOSFETs in 4H-SiC,” Materials Science Forum, Vol. 924, pp. 752-755, 2018.

C. Jiao, R. Ramamurthy, D. Zemlyanov, D. Morisette, “A High Quality, Thermal-Oxidation-Free MOS Interface Formed by ALD SiO2 Deposition on Silicon Oxynitride Terminated 4H-SiC,” presented at the 60th Electronic Materials Conference (EMC 2018), June 27-29, 2018.

I. Jayawardhena, A. Jayawardena, C. Jiao, D. Morisette, S. Dhar, “Characterization of near-interface traps at dielectric/SiC interfaces using CCDLTS,” presented at the 12th European Conference on Silicon Carbide and Related Materials (ESCRM 2018), September 2-6, 2018.

R. P. Ramamurthy, D. T. Morisette, V. Amarasinghe, L. C. Feldman, “Thermal-oxidation-free dielectrics for SiC power devices,” presented at the 2017 IEEE 5th Workshop on Wide-Bandgap Power Devices and Applications (WiPDA), Albuquerque, NM, October 30 – November 1, 2017, p. 242-5.

S. Swandono, D. Morisette, J. A. Cooper, “Effect of Non-linearity and Energy-Dependence Phenomena on AC MOS Conductance Technique,” poster presented at the 46th IEEE Semiconductor Interface Specialists Conference, Arlington, VA, Dec 2-5, 2015.

C. Jiao, A.C. Ahyi, C. Xu, D. Morisette, L.C. Feldman and S. Dhar, “Variation of interfacial phosphorus concentration on 4H‐SiC MOS devices with phosphosilicate glass gate dielectric,” Paper presented at the 16th International Conference on Silicon Carbide and Related Materials, Giardini-Naxos, Italy, October 4-9, 2015. Proceedings to be published in Material Science Forum.

C. Jiao, A. C. Ahyi, C. Xu, D. Morisette, L. C. Feldman and S. Dhar “Correlation between Interfacial Phosphorus Coverage and Electrical Properties of 4H-SiC MOS Devices with PSG Gate Dielectric,” Paper presented at the 57th Electronic Materials Conference, Columbus, Ohio, June 24-26, 2015.

D. T. Morisette, and J. A. Cooper, “Performance of SiC Bipolar (PiN) and Unipolar (SBD) Power Rectifiers in Current-Voltage-Frequency Parameter Space,” Materials Science Forum, Vols. 389-393, April 2002, pp. 1133-1136.

D. T. Morisette, and J. A. Cooper, “Impact of Material Defects on SiC Schottky Barrier Diodes,” Materials Science Forum, Vols. 389-393, April 2002, pp. 1133-1136.

D. T. Morisette, and J. A. Cooper, “High-Voltage Pulse Instabilities in SiC Schottky Diodes with Implanted Resistive Edge Terminations,” Materials Science Forum, Vols. 389-393, April 2002, pp. 1157-1160.

H. M. McGlothlin, D. T. Morisette, J. A. Cooper, Jr., M. R. Melloch, “4 kV Silicon Carbide Schottky Diodes for High-frequency Switching Applications,” 57th Annual Device Research Conference Digest, June 1999, pp. 42-43.

J. A. Cooper, S. H. Ryu, Y. Li, M. Matin, J. Spitz, D. T. Morisette, H.M. McGlothlin, M. K. Das, M. R. Melloch, M. A. Capano, J. M. Woodall, “SiC power electronic devices, MOSFETs and rectifiers,” MRS Proceedings, Vol. 572, No. 3, April 1999, pp. 3-14.

I. U. Jayawardhena, R. P. Ramamurthy, D. Morisette, A. C. Ahyi, R. Thorpe, M. A. Kuroda, L.C. Feldman, S. Dhar, “Effect of surface treatments on ALD Al2O3/4H-SiC metal–oxide–semiconductor field-effect transistors,” Journal of Applied Physics, Vol. 129, No. 7, p. 075702, February 2021. [LINK]

R. P. Ramamurthy, N. Islam, M. Sampath, D. T. Morisette, J. A. Cooper, “The Tri-Gate MOSFET: A New Vertical Power Transistor in 4H-SiC,” IEEE Electron Device Letters, Vol. 42, No. 1, pp. 90-93, January 2021. [LINK]

C. J. Klingshirn, A. Jayawardena, S. Dhar, R. P. Ramamurthy, D. Morisette, Z. Warecki, J. Cumings, T. Zheleva, A. Lelis, L. G. Salamanca-Riba, “Electron beam-induced crystallization of Al2O3 gate layer on β-Ga2O3 MOS Capacitors,” Micron, Vol. 140, 102954, January 2021. [LINK]

N. Opondo, J. A. Cooper, H. J. Liao, W. N. Chen, D. Morisette, “The Waffle Substrate: A Novel Approach to Reducing Substrate Resistance in SiC Power Devices,” Materials Science Forum, Vol. 1004, pp. 738-746, July 2020. [LINK]

M. Sampath, A. Salemi, D. Morisette, J. A. Cooper, “The IMOSFET: A Deeply-Scaled Fully-Self-Aligned Trench MOSFET,” Materials Science Forum, Vol. 1004, pp. 751-757, July 2020. [LINK]

J. A. Cooper, D. T. Morisette, “Performance limits of vertical unipolar power devices in GaN and 4H-SiC,” IEEE Electron Device Letters, Vol. 41, No. 6, pp. 892-895, June 2020. [LINK]

B. Chatterjee, C. Mousoulis, D. H. Seo, A. Kumar, S. Maity, S. M. Scott, D. J. Valentino, D. T. Morisette, D. Peroulis, S. Sen, “A Wearable Real-Time CMOS Dosimeter With Integrated Zero-Bias Floating Gate Sensor and an 861-nW 18-Bit Energy-Resolution Scalable Time-Based Radiation to Digital Converter,” IEEE Journal of Solid-State Circuits, accepted for publication, December 2019.

Md. M. Alam, J. A. Cooper, D. T. Morisette, “Design Guidelines for Superjunction Devices in the Presence of Charge Imbalance,” IEEE Transactions on Electron Devices, Vol. 65, No. 8, August 2018, p. 3345.

A. Jayawardena, R. P. Ramamurthy, A. C. Ahyi, D. Morisette, S. Dhar, “Interface trapping in (-201) β-Ga2O3 MOS capacitors with deposited dielectrics,” Applied Physics Letters, Vol. 112, No 19, May 2018, p. 192108.

C. Jiao, A. C. Ahyi, S. Dhar, D. Morisette, R. Myers-Ward, “Interface Trap Profiles in 4H- and 6H-SiC MOS Capacitors with Nitrogen- and Phosphorus-Doped Gate Oxides,” Journal of Electronic Materials, Vol. 46, No. 4, April 2017, p. 2296.

C. Jiao, A. C. Ahyi, C. Xu, D. Morisette, L. C. Feldman, and S. Dhar, “Phospho-silicate glass gated 4H-SiC MOS devices: phosphorus concentration dependence,” Journal of Applied Physics, Vol. 119, No. 15, April 2016, p. 155705.

M. A. Capano, B. M. Capano, D. T. Morisette, A. Salleo, S. Lee, and M. F. Toney, “High-resolution X-ray Analysis of Graphene Grown on 4H–SiC (000) at low pressures,” Journal of Materials Research, Vol. 29, No. 3, February 2014, pp. 439-446.

K. Park, N. Kim, D. T. Morisette, N. R. Aluru, R. Bashir, “Resonant MEMS Mass Sensors for Measurement of Microdroplet Evaporation,” Journal of Microelectromechanical Systems, Vol. 21, No. 3, June 2012, pp. 702-711.

E. Salm, Y. S. Liu, D. Marchwiany, D. Morisette, Y. He, L. Razouk, A. K. Bhunia, R. Bashir, “Electrical Detection of dsDNA and Polymerase Chain Reaction Amplification,” Biomed Microdevices, Vol 13, No. 6, December 2011, pp. 973-82.

S. Bhattacharya, S. Salamat, D. T. Morisette, P. Banada, D. Akin, Y. S. Liu, A. K. Bhunia, M. Ladisch, R. Bashir, “PCR-Based Detection in a Micro-Fabricated Platform,” Lab on a Chip, Vol. 8, No. 7, July 2008, pp. 1130-1136.

R. Gómez-Sjöberg, D. T. Morisette, R. Bashir, “Impedance Microbiology-on-a-Chip: Microfluidic Bioprocessor for Rapid Detection of Bacterial Metabolism,” Journal of Microelectromechanical Systems, Vol. 14 No. 4, August 2005, pp. 829-838.

O. H. Elibol, D. T. Morisette, D. Akin, J. P. Denton, and R. Bashir, “Integrated Nanoscale Silicon Sensors Using Top-Down Fabrication,” Applied Physics Letters, Vol. 83, No. 22, December 2003, pp. 4613-4615.

D. T. Morisette, and J. A. Cooper, “Theoretical Comparison of SiC PiN and Schottky Diodes Based on Power Dissipation Considerations,” IEEE Transactions on Electron Devices, Vol. 49, No. 9, September 2001, pp. 349-352.

D. T. Morisette, G. M. Dolny, J. A. Cooper, M. R. Melloch, P. M. Shenoy, M. Zafrani, J. Gladish, “Static and Dynamic Characterization of Large-Area High-Current-Density SiC Schottky Diodes,” IEEE Transactions on Electron Devices, Vol. 48, No. 2, February 2001, pp. 349-52.

J. A. Cooper, D. T. Morisette, M. Sampath, “MOS devices with increased short circuit robustness”, U.S. Patent Application No. 16/438,055 submitted Dec 19, 2019.

A. Salemi, D. T. Morisette, J. A. Cooper, “Angled Trench SiC UMOSFET,” patent disclosure submitted Feb 2, 2018.

D. T. Morisette, R. P. Ramamurthy, “Silicon carbide power transistor apparatus and method of producing same,” U.S. Patent Application No. 15/894,911 (filed February 12, 2018).

R. Bashir, L. R. Razouk, D. T. Morisette, B. Erimli, “Apparatus and method for detecting live cells with an integrated filter and growth detection device.” U. S. Patent Nos. 7,816,100 (December 19, 2010), 7,553,633 (June 30, 2009), and 7,413,891 (August 19, 2008).