Publications

Conference Papers

1. R. Venkatesan, S. Ramasubramanium, S. Venkataramani, K. Roy, and A. Raghunathan, "STAG: Spintronic-Tape Architecture for GPGPU Cache Hierarchies," International Symposium on Computer Architecture (ISCA), June 2014.

2. R. Venkatesan, M. Sharad, K. Roy and A. Raghunathan, "DWM-TAPESTRI: An Energy-efficient All-Spin Cache using Domain Wall Shift based Writes," IEEE/ACM Design, Automation, and Test in Europe (DATE), March 2013.

3. R. Venkatesan, V. Kozhikkottu, C. Augustine, A. Raychowdhury, K. Roy and A. Raghunathan, "TapeCache: A High Density, Energy Efficient Cache based on Domain Wall Memory" IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), July- August 2012 (Best Paper Award).

4. R. Venkatesan, A. Agarwal, K. Roy, and A. Raghunathan, "MACACO: Modeling and Analysis of Circuits for Approximate Computing," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2011.

5. R. Venkatesan, V. Chippa, C. Augustine, A. Raghunathan, and K. Roy, "Energy Efficient Many-core Processor for Recognition and Mining using Spin-based Memory," IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), June 2011.

6. S. Ramasubramanium, R. Venkatesan, M. Sharad, K.Roy, and A. Raghunathan, "SPINDLE: SPINtronic Deep Learning Engine for Large-scale Neuromorphic Computing," IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), September 2014.

7. M. Sharad, R. Venkatesan, X. Fong, A. Raghunathan, and K. Roy, "Energy-Efficient MRAM Access Scheme Using Hybrid Circuits Based on Spin-Torque Sensors," IEEE Sensors, November 2013.

8. M. Sharad, R. Venkatesan, A. Raghunathan, and K. Roy, "Multi-level Magnetic RAM using Domain wall Shift for Energy-Efficient, High-Density Caches," IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), September 2013.

9. M. Sharad, R. Venkatesan, X. Fong, A. Raghunathan, K. Roy, "Reading Spin-Torque Memory with Spin-Torque Sensors," IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), July 2013.

10. M. Sharad, R. Venkatesan, A. Raghunathan, and K. Roy, "Domain-wall Shift based Multi-Level MRAM for High-speed, High-density and Energy-efficient Caches," IEEE/ACM Device Research Conference (DRC), June 2013.

11. V. Kozhikkottu, R. Venkatesan, A. Raghunathan, and S. Dey, "VESPA: Variability Emulation for System-on-chip Performance Analysis," IEEE/ACM Design, Automation, and Test in Europe (DATE), March 2011.

Journal Papers

1. R. Venkatesan, M. Sharad, V. J. Kozhikottu, C. Augustine, A. Raychowdhury, K. Roy, and A. Raghunathan, "Cache Design with Domain Wall Memory," IEEE Transactions on Computers. (Accepted for publication)

2. R. Venkatesan, V. Chippa, C. Augustine, A. Raghunathan, and K. Roy, "Domain-Specific Many-core Computing using Spin-based Memory," IEEE Transactions on Nanotechnology. (Accepted for publication).

3. X. Fong, R. Venkatesan, A. Raghunathan, and K. Roy, "Non-volatile Complementary Polarizer Spin-Transfer Torque (CPSTT) On-chip Caches: A Device/Circuit/Systems Perspective," IEEE Transactions on Magnetics. (Accepted for publication).

4. B. Raj, J. Mitra, D. K. Bihani, R. Venkatesan, A.K. Saxena, S. Dasgupta, "Process Variation Tolerant FinFET Based Robust Low Power SRAM Cell Design at 32 nm Technology," Journal of Low Power Electronics (JOLPE), April 2011.