Journals (10)
"High-Performance Complementary III-V Tunnel FETs with Strain Engineering"
arXiv:1605.009552016Not Cited Yet
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0
"Atomistic Modeling trap-assisted tunneling in hole tunnel FETs"
Journal of Applied Physics 123 (2018);doi: 10.1063/1.50187372018Not Cited Yet
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"A Multiscale Modeling of Triple-Heterojunction Tunneling FETs"
IEEE Transactions on Electron Devices, Volume: 64, Issue: 6, Pages: 2728 - 2735, June 2017;doi:10.1109/TED.2017.26906692017Not Cited Yet
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"High-Current Tunneling FETs With ( 1\bar {1}0 ) Orientation and a Channel Heterojunction"
IEEE Electron Device Letters, Volume:37 , Issue: 3, Page(s): 345 - 348, March 2016;doi:10.1109/LED.2016.25232692016Not Cited Yet
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"Performance degradation of superlattice MOSFETs due to scattering in the contacts"
Journal of Applied Physics, Vol 120, 224501, December 2016;doi: 10.1063/1.49713412016Not Cited Yet
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"Scalable GaSb/InAs tunnel FETs with non-uniform body thickness"
IEEE Transactions on Electron Devices, Volume: 64, Issue: 1, Pages: 96 - 101, Jan. 2017;doi: 10.1109/TED.2016.26247442016Not Cited Yet
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"P-Type Tunnel FETs With Triple Heterojunctions"
IEEE Journal of the Electron Devices Society, Volume: 4, Issue: 6, Page(s): 410 - 415, Nov. 2016;doi:10.1109/JEDS.2016.26149152016Not Cited Yet
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"Design and Simulation of GaSb/InAs 2D Transmission-Enhanced Tunneling FETs"
IEEE ELECTRON DEVICE LETTERS, VOL: 37, Issue: 1, Pages: 107 - 110, JANUARY 2016;doi:10.1109/LED.2015.24976662016Not Cited Yet
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"Design and Simulation of Two-dimensional Superlattice Steep Transistors"
IEEE ELECTRON DEVICE LETTERS., vol. 35, Issue: 12, Page(s): 1212 - 1214, Dec. 2014;doi:10.1109/LED.2014.236459320140
2
"Atomistic simulation of phonon and alloy limited hole mobility in Si1-xGex nanowires"
Phys. Status Solidi RRL 7, No. 10, 903–906 (2013) 20130
3
Proceedings (9)
"Sb- and Al-free ultra-high-current tunnel FET designs"
Proceedings of the 2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S), Pages 1-32017Not Cited Yet
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"A high-current InP-channel triple heterojunction tunnel transistor design "
Proceedings of the 75th Device Research Conference (DRC), University of Notre Dame (Indiana, USA) from June 25-28, 2017;doi:10.1109/DRC.2017.79994372017Not Cited Yet
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"A Tunnel FET Design for High-Current, 120 mV Operation"
2016 IEEE International Electron Devices Meeting, December 3-7, 2016, San Francisco, CA;doi:10.1109/IEDM.2016.78385112016Not Cited Yet
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"Exploring Channel Doping Designs for High-Performance Tunneling FETs"
Device Research Conference (DRC), June, 2016, Newark, Delaware, USA;doi:10.1109/DRC.2016.75484562016Not Cited Yet
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"Extremely high simulated ballistic currents in triple-heterojunction tunnel transistors"
Device Research Conference (DRC), June, 2016, Newark, Delaware, USA;doi:10.1109/DRC.2016.75484242016Not Cited Yet
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"High-Current InP-Based Triple Heterojunction Tunnel Transistors"
28th International Conference on Indium Phosphide and Related Materials (IPRM), June, 2016, Toyama, Japan;doi:10.1109/ICIPRM.2016.75285922016Not Cited Yet
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"Record-Performance Thermally-Limited Devices, Prospects for High-On-Current Steep Subthreshold Swing Devices"
2015 Conference on Indium Phosphide and Related Matrerials, June 8-July 2, Santa Barbara, CA2015Not Cited Yet
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"Comparison of Ultra-Thin InAs and InGaAs Quantum Wells and Ultra-Thin-Body Surface-Channel MOSFETs"
27th International Conference on Indium Phosphide and Related Materials, June 28-July 2, 2015 University of California Santa Barbara, CA, USA2015Not Cited Yet
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"Transistors for VLSI, for Wireless: A View Forwards Through Fog"
73rd Device Research Conference (DRC), Ohio State University,June 21-24, 20152015Not Cited Yet
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Conferences (11)
"Sb- and Al- Free Ultra-High-Current Tunnel FET Design"
Fifth Berkeley Symposium on Energy Efficient Electronic Systems and Steep Transistors Workshop October 19-20, 2017 University of California, Berkeley, California, USA20170
0
"Sb- and Al-free ultra-high-current tunnel FET designs"
2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S), Berkeley, California, October 19-20, 201720170
0
"A high-current InP-channel triple heterojunction tunnel transistor design"
75th Device Research Conference (DRC), University of Notre Dame (Indiana, USA) from June 25-28, 201720170
0
"Extremely high simulated ballistic currents in triple-heterojunction tunnel transistors"
Device Research Conference (DRC), June, 2016, Newark, Delaware, USA20160
0
"Exploring Channel Doping Designs for High-Performance Tunneling FETs"
Device Research Conference (DRC), June, 2016, Newark, Delaware, USA20160
0
"A Tunnel FET Design for High-Current, 120 mV Operation"
IEEE International Electron Devices Meeting, December 3-7, 2016, San Francisco20160
0
"Multiscale Transport Simulation of Nanoelectronic Devices with NEMO5"
Progress In Electromagnetics Research Symposium (PIERS), August, 2016, Shanghai, China20160
0
"Computational Study of Strain-Engineered III-V Tunneling Transistors"
Progress In Electromagnetics Research Symposium (PIERS), August, 2016, Shanghai, China20160
0
"High-Current InP-Based Triple Heterojunction Tunnel Transistors"
28th International Conference on Indium Phosphide and Related Materials (IPRM), June, 2016, Toyama, Japan20160
0
"STEEP Transistor Modeling with NEMO5"
Steep Transistors Workshop, University of Notre Dame, Notre Dame, IN, October 5-6, 201520150
0
"Transistors for VLSI, for Wireless: A View Forwards Through Fog"
73rd Device Research Conference (DRC), Ohio State University,June 21-24, 201520150
0