Journals (10)
"High-Performance Complementary III-V Tunnel FETs with Strain Engineering"
arXiv:1605.009552016Not Cited Yet
"Atomistic Modeling trap-assisted tunneling in hole tunnel FETs"
Journal of Applied Physics 123 (2018);doi: 10.1063/1.50187372018Not Cited Yet
"A Multiscale Modeling of Triple-Heterojunction Tunneling FETs"
IEEE Transactions on Electron Devices, Volume: 64, Issue: 6, Pages: 2728 - 2735, June 2017;doi:10.1109/TED.2017.26906692017Not Cited Yet
"High-Current Tunneling FETs With ( 1\bar {1}0 ) Orientation and a Channel Heterojunction"
IEEE Electron Device Letters, Volume:37 , Issue: 3, Page(s): 345 - 348, March 2016;doi:10.1109/LED.2016.25232692016Not Cited Yet
"Performance degradation of superlattice MOSFETs due to scattering in the contacts"
Journal of Applied Physics, Vol 120, 224501, December 2016;doi: 10.1063/1.49713412016Not Cited Yet
"Scalable GaSb/InAs tunnel FETs with non-uniform body thickness"
IEEE Transactions on Electron Devices, Volume: 64, Issue: 1, Pages: 96 - 101, Jan. 2017;doi: 10.1109/TED.2016.26247442016Not Cited Yet
"P-Type Tunnel FETs With Triple Heterojunctions"
IEEE Journal of the Electron Devices Society, Volume: 4, Issue: 6, Page(s): 410 - 415, Nov. 2016;doi:10.1109/JEDS.2016.26149152016Not Cited Yet
"Design and Simulation of GaSb/InAs 2D Transmission-Enhanced Tunneling FETs"
IEEE ELECTRON DEVICE LETTERS, VOL: 37, Issue: 1, Pages: 107 - 110, JANUARY 2016;doi:10.1109/LED.2015.24976662016Not Cited Yet
"Design and Simulation of Two-dimensional Superlattice Steep Transistors"
IEEE ELECTRON DEVICE LETTERS., vol. 35, Issue: 12, Page(s): 1212 - 1214, Dec. 2014;doi:10.1109/LED.2014.23645932014
"Atomistic simulation of phonon and alloy limited hole mobility in Si1-xGex nanowires"
Phys. Status Solidi RRL 7, No. 10, 903–906 (2013) 2013
Proceedings (9)
"Sb- and Al-free ultra-high-current tunnel FET designs"
Proceedings of the 2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S), Pages 1-32017Not Cited Yet
"A high-current InP-channel triple heterojunction tunnel transistor design "
Proceedings of the 75th Device Research Conference (DRC), University of Notre Dame (Indiana, USA) from June 25-28, 2017;doi:10.1109/DRC.2017.79994372017Not Cited Yet
"A Tunnel FET Design for High-Current, 120 mV Operation"
2016 IEEE International Electron Devices Meeting, December 3-7, 2016, San Francisco, CA;doi:10.1109/IEDM.2016.78385112016Not Cited Yet
"Exploring Channel Doping Designs for High-Performance Tunneling FETs"
Device Research Conference (DRC), June, 2016, Newark, Delaware, USA;doi:10.1109/DRC.2016.75484562016Not Cited Yet
"Extremely high simulated ballistic currents in triple-heterojunction tunnel transistors"
Device Research Conference (DRC), June, 2016, Newark, Delaware, USA;doi:10.1109/DRC.2016.75484242016Not Cited Yet
"High-Current InP-Based Triple Heterojunction Tunnel Transistors"
28th International Conference on Indium Phosphide and Related Materials (IPRM), June, 2016, Toyama, Japan;doi:10.1109/ICIPRM.2016.75285922016Not Cited Yet
"Record-Performance Thermally-Limited Devices, Prospects for High-On-Current Steep Subthreshold Swing Devices"
2015 Conference on Indium Phosphide and Related Matrerials, June 8-July 2, Santa Barbara, CA2015Not Cited Yet
"Comparison of Ultra-Thin InAs and InGaAs Quantum Wells and Ultra-Thin-Body Surface-Channel MOSFETs"
27th International Conference on Indium Phosphide and Related Materials, June 28-July 2, 2015 University of California Santa Barbara, CA, USA2015Not Cited Yet
"Transistors for VLSI, for Wireless: A View Forwards Through Fog"
73rd Device Research Conference (DRC), Ohio State University,June 21-24, 20152015Not Cited Yet
Conferences (11)
"Sb- and Al- Free Ultra-High-Current Tunnel FET Design"
Fifth Berkeley Symposium on Energy Efficient Electronic Systems and Steep Transistors Workshop October 19-20, 2017 University of California, Berkeley, California, USA2017
"Sb- and Al-free ultra-high-current tunnel FET designs"
2017 Fifth Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop (E3S), Berkeley, California, October 19-20, 20172017
"A high-current InP-channel triple heterojunction tunnel transistor design"
75th Device Research Conference (DRC), University of Notre Dame (Indiana, USA) from June 25-28, 20172017
"Extremely high simulated ballistic currents in triple-heterojunction tunnel transistors"
Device Research Conference (DRC), June, 2016, Newark, Delaware, USA2016
"Exploring Channel Doping Designs for High-Performance Tunneling FETs"
Device Research Conference (DRC), June, 2016, Newark, Delaware, USA2016
"A Tunnel FET Design for High-Current, 120 mV Operation"
IEEE International Electron Devices Meeting, December 3-7, 2016, San Francisco2016
"Multiscale Transport Simulation of Nanoelectronic Devices with NEMO5"
Progress In Electromagnetics Research Symposium (PIERS), August, 2016, Shanghai, China2016
"Computational Study of Strain-Engineered III-V Tunneling Transistors"
Progress In Electromagnetics Research Symposium (PIERS), August, 2016, Shanghai, China2016
"High-Current InP-Based Triple Heterojunction Tunnel Transistors"
28th International Conference on Indium Phosphide and Related Materials (IPRM), June, 2016, Toyama, Japan2016
"STEEP Transistor Modeling with NEMO5"
Steep Transistors Workshop, University of Notre Dame, Notre Dame, IN, October 5-6, 20152015
"Transistors for VLSI, for Wireless: A View Forwards Through Fog"
73rd Device Research Conference (DRC), Ohio State University,June 21-24, 20152015