Journals (33)
"Doping Profile Engineered Triple Heterojunction TFETs With 12-nm Body Thickness"
IEEE Transactions on Electron Devices, June 2021, Vol. 68, No. 6, Pages 3104-3111;doi: 10.1109/TED.2021.30751902021Not Cited Yet
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0
"WSe2 Homojunction Devices: Electrostatically Configurable as Diodes, MOSFETs, and Tunnel FETs for Reconfigurable Computing"
Small, Vol. 15, Issue 14 (2019);doi:10.1002/smll.2019027702019Not Cited Yet
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0
"Theoretical study of strain-dependent optical absorption in doped Stranski-Krastanov grown InAs/InGaAs/GaAs/AlGaAs quantum dots"
Beilstein Journal of Nanotechnology, 2018, 9, 1075–1084;doi:10.3762/bjnano.9.992018Not Cited Yet
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0
"Channel Thickness Optimization for Ultrathin and 2-D Chemically Doped TFETs"
IEEE Transactions on Electron Devices, 2018, Vol. 65, No. 10, Pages 4614-4621;doi: 10.1109/TED.2018.28624082018Not Cited Yet
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0
"Sensitivity Challenge of Steep Transistors"
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 65, NO. 4, APRIL 2018;doi:10.1109/TED.2018.28080402018Not Cited Yet
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0
"Robust Mode Space Approach for Atomistic Modeling of Realistically Large Nanowire Transistors"
Journal of Applied Physics 123, 044303 (2018);doi:10.1063/1.50102382018Not Cited Yet
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0
"Complementary Black Phosphorus Tunneling Field-Effect Transistors"
ACS Nano, Publication Date (Web): December 18, 2018;doi: 10.1021/acsnano.8b064412018Not Cited Yet
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0
"Alloy Engineered Nitride Tunneling Field Effect Transistor: A solution for the challenge of heterojunction TFETs"
IEEE Transactions on Electron Devices, 2018 (Early Access);doi: 10.1109/TED.2018.28777532018Not Cited Yet
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0
"Switching Mechanism and the Scalability of vertical-TFETs"
, 2018, Vol. 65, No. 7, Pages 3065-30682018Not Cited Yet
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0
"Dramatic Impact of Dimensionality on the Electrostatics of P-N Junctions and Its Sensing and Switching Applications"
IEEE Transactions on Nanotechnology, 2018, Vol. 17, No. 2, Pages 293-2982018Not Cited Yet
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0
"Transport in vertically stacked hetero-structures from 2D materials"
IOP Journal of Physics: Conf. Series 864 (2017) 012053;doi:10.1088/1742-6596/864/1/0120532017Not Cited Yet
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"Combination of Equilibrium and Nonequilibrium Carrier Statistics Into an Atomistic Quantum Transport Model for Tunneling Heterojunctions"
IEEE Transactions on Electron Devices, Vol: 64, Issue: 6, Page(s): 2512 - 2518, June 2017;doi:10.1109/TED.2017.26906262017Not Cited Yet
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"A Multiscale Modeling of Triple-Heterojunction Tunneling FETs"
IEEE Transactions on Electron Devices, Volume: 64, Issue: 6, Pages: 2728 - 2735, June 2017;doi:10.1109/TED.2017.26906692017Not Cited Yet
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0
"Thickness Engineered Tunnel Field-Effect Transistors based on Phosphorene"
IEEE Electron Device Letters, Volume: 38, Issue: 1, Jan. 2017, Pages: 130 - 133;doi: 10.1109/LED.2016.26275382016Not Cited Yet
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0
"Unfolding and effective bandstructure calculations as discrete real-and reciprocal-space operations"
Physica B: Condensed Matter, Volume 491, 15 June 2016, Pages 22–30;doi:10.1016/j.physb.2016.03.0112016Not Cited Yet
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0
"Saving Moore's Law Down To 1nm Channels With Anisotropic Effective Mass"
Scientific Reports 6, Article number: 31501 ;doi: 10.1038/srep31501 (2016)2016Not Cited Yet
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0
"Optimum High-k Oxide for the Best Performance of Ultra-scaled Double-Gate MOSFETs"
IEEE Transactions on Nanotechnology (2016);doi:10.1109/TNANO.2016.25834112016Not Cited Yet
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0
"Few-layer Phosphorene: An Ideal 2D Material For Tunnel Transistors"
Scientific Reports 6, Article number: 28515 (2016);doi:10.1038/srep285152016Not Cited Yet
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0
"Design Rules for High Performance Tunnel Transistors from 2D Materials"
IEEE Journal of Electron Device Society (J-EDS), Volume: 4, Issue: 5, Page(s): 260 - 265, Sept. 2016 ;doi:10.1109/JEDS.2016.25682192016Not Cited Yet
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"From Fowler-Nordheim to Non-Equilibrium Green's Function Modeling of Tunneling"
IEEE Transactions on Electron Devices, Volume:63 , Issue: 7, July 2016;doi:10.1109/TED.2016.25655822016Not Cited Yet
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0
"Configurable Electrostatically Doped High Performance Bilayer Graphene Tunnel FET"
IEEE Journal of the Electron Devices Society, Volume:4 ,Issue: 3, Page(s): 124 - 128, May 2016;doi:10.1109/JEDS.2016.25399192015Not Cited Yet
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0
"Universal Behavior of Atomistic Strain in Self-Assembled Quantum Dots"
IEEE JOURNAL OF QUANTUM ELECTRONICS, vol. 52, no. 7, july 2016;doi:10.1109/JQE.2016.25739592015Not Cited Yet
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0
"Theoretical study of strain-dependent optical absorption in Stranski-Krastanov grown InAs/InGaAs/GaAs/AlGaAs quantum dots"
arXiv:1502.077262015Not Cited Yet
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0
"Polarization-Engineered III-Nitride Heterojunction Tunnel Field-Effect Transistors"
IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, Volume:1, Pages: 28 - 34, Dec. 2015;doi:10.1109/JXCDC.2015.242643320150
5
"Tunnel field effect transistors in two dimensional transition metal dichalcogenides"
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 1, Page(s):12-18 , 14 April 2015 ;doi:10.1109/JXCDC.2015.24230962015Not Cited Yet
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0
"Can Homojunction Tunnel FETs Scale Below 10nm?"
IEEE ELECTRON DEVICE LETTERS, vol. 37, Issue: 1, Page(s): 115-118, January, 2016;doi:10.1109/LED.2015.25018202015Not Cited Yet
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"Design Guidelines for Sub-12 nm Nanowire MOSFETs"
IEEE Transactions on Nanotechnology, vol. 14, Issue: 2, Page(s): 210 - 213, March 2015;doi: 10.1109/TNANO.2015.239544120150
15
"Electrically Tunable Bandgaps in Bilayer MoS2"
Nano Lett., 2015, 15 (12), pp 8000–80072015Not Cited Yet
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0
"A predictive analytic model for high-performance tunneling field-effect transistors approaching non-equilibrium Green's function simulations"
Journal of Applied Physics, 118, 164305 (2015);doi:10.1063/1.4934682A2015Not Cited Yet
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0
"Dielectric Engineered Tunnel Field-Effect Transistor"
IEEE ELECTRON DEVICE LETTERS, vol. 36, Issue: 10, Page(s): 1097-1100, October, 2015;doi:10.1109/LED.2015.24741472015Not Cited Yet
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0
"Scaling Theory of Electrically Doped 2D Transistors"
IEEE Electron Device Letters, vol. 36, Issue: 7, Page(s): 726-728, July 2015;doi:10.1109/LED.2015.243635620150
2
"Brillouin zone unfolding method for effective phonon spectra"
Physical Review B 90, 205214 (2014);doi:10.1103/PhysRevB.90.20521420140
1
"Efficient and realistic device modeling from atomic detail to the nanoscale"
Journal of Computational Electronics December 2013, Volume 12, Issue 4, pp 592-600;doi:10.1007/s10825-013-0509-020130
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Proceedings (16)
"III-N heterostructure devices for low-power logic"
Proceedings of the Semiconductor Technology International Conference (CSTIC), 2017 China, Pages 1-3;doi:10.1109/CSTIC.2017.79197432017Not Cited Yet
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"Novel III-N heterostructure devices for low-power logic and more"
Nanotechnology (IEEE-NANO), 2016 IEEE 16th International Conference on(pp. 767-769). IEEE;doi:10.1109/NANO.2016.77513362016Not Cited Yet
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0
"Extremely high simulated ballistic currents in triple-heterojunction tunnel transistors"
Device Research Conference (DRC), June, 2016, Newark, Delaware, USA;doi:10.1109/DRC.2016.75484242016Not Cited Yet
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0
"Transport in vertically stacked hetero-structures from 2D materials"
33rd International Conference on the Physics of Semiconductors, Beijing, China on July 31- August 5, 2016 2016Not Cited Yet
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0
"Tunneling: The Major Issue in Ultra-scaled MOSFETs"
IEEE Nano, Rome, Italy, July 26-30, 2015, Pages: 670 - 673;doi:10.1109/NANO.2015.73886942015Not Cited Yet
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"Engineering The Optical Transitions of Self-Assembled Quantum Dots"
International Workshop on Computational Electronics (IWCE 2015) September 2, 2015 West Lafayette, Indiana USA, Pages: 1 - 4;doi:10.1109/IWCE.2015.73019402015Not Cited Yet
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0
"Mode space tight binding model for ultra-fast simulations of III-V nanowire MOSFETs and heterojunction TFETs"
International Workshop on Computational Electronics (IWCE 2015) September 2, 2015 West Lafayette, Indiana USA, Page(s): 1 - 3;doi:10.1109/IWCE.2015.73019342015Not Cited Yet
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"2D tunnel transistors for ultra-low power applications: Promises and challenges"
2015 Fourth Berkeley Symposium on Energy Efficient Electronic Systems (E3S), 1-2 Oct. 2015, Berkeley, CA, Page(s): 1 - 3;doi:10.1109/E3S.2015.73367922015Not Cited Yet
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0
"Electrically doped WTe2 tunnel transistors"
2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 9-11 Sept. 2015, Washington, DC, Page(s): 270 - 272;doi:10.1109/SISPAD.2015.72923112015Not Cited Yet
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"Quantum dot lab: an online platform for quantum dot simulations"
International Workshop on Computational Electronics (IWCE), 2015, Page(s): 1 - 3;doi:10.1109/IWCE.2015.73019822015Not Cited Yet
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0
"Electrically Doped 2D matertial tunnel transistor"
International Workshop on Computational Electronics (IWCE 2015) September 2, 2015 West Lafayette, Indiana USA, Pages: 1 - 3;doi:10.1109/IWCE.2015.73019662015Not Cited Yet
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"Achieving a higher performance in bilayer graphene FET - strain engineering"
the 20th International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Washington DC, 9-11 Sep. 2015, Pages: 177 - 181;doi:10.1109/SISPAD.2015.72922882015Not Cited Yet
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0
"Atomistic simulation of steep subthreshold slope Bi-layer MoS2 transistors"
2014 IEEE Silicon Nanoelectronics Workshop (SNW), 8-9 June 2014, Honolulu, HI, Page(s): 1 - 2;doi:10.1109/SNW.2014.73486062014Not Cited Yet
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"Optimization of the anharmonic strain model to capture realistic strain distributions in quantum dots"
14th IEEE International Conference on Nanotechnology, 18-21 Aug. 2014, Page(s): 921 - 924, Toronto, ON;doi: 10.1109/NANO.2014.69681372014Not Cited Yet
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0
"Atomistic Simulation of GaN/InN/GaN Tunnel FETs"
Berkeley Symposium on Energy Efficient Electronic Systems, 20132013Not Cited Yet
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0
"NEMO5, a Parallel, Multiscale, Multiphysics Nanoelectronics Modeling Tool"
IEEE SISPAD 2012, pg: 388-391, International Conference on Simulation of Semiconductor Processes and Devices, Denver, CO, Sept. 201220120
1
Conferences (34)
"NEMO5, a Parallel, Multiscale, Multiphysics Nanoelectronics Modeling Tool From Basic Physics to Real Devices and to Global Impact on nanoHUB.org"
Korea Advanced Institute of Science and Technology (KAIST), Daejeon, July 6 2018, Host Prof. Mincheol Shin20180
0
"Optimizing the Device Structure of 2D Material Tunnel FETs"
TECHCON 2017, Renaissance Hotel in Austin, Texas, September 10-12, 201720170
0
"Novel steep transistors"
StarNET E-Workshop, Purdue University, IN, USA (2016)20160
0
"Extremely high simulated ballistic currents in triple-heterojunction tunnel transistors"
Device Research Conference (DRC), June, 2016, Newark, Delaware, USA20160
0
"The Influence Of Carrier Thermalization On The Performance Of Nitride Tunneling Hetero-Structures"
TECH CON 2016, Sept. 11 - Tuesday, Sept. 13, 2016, Renaissance Austin Hotel, Austin, TX, United States20160
0
"Why Do We Need Novel Steep Transistors?"
TECH CON 2016, Sept. 11 - Tuesday, Sept. 13, 2016, Renaissance Austin Hotel, Austin, TX, United States20160
0
"Transport in vertically stacked hetero-structures from 2D materials"
33rd International Conference on the Physics of Semiconductors, Beijing, China on July 31- August 5, 2016 20160
0
"Atomistic Modeling of Interlayer TFETs"
2016 LEAST review, August 10 & 11, 2016, University of Notre Dame20160
0
"Atomistic Modeling of WTe-MoS2 Interlayer TFETs"
TECH CON 2016, Sept. 11 - Tuesday, Sept. 13, 2016, Renaissance Austin Hotel, Austin, TX, United States20160
0
"Novel III-N heterostructure devices for low-power logic and more"
2016 IEEE 16th International Conference on Environment and Electrical Engineering, Florence, Italy, 2016 20160
0
"2D crystal TFETs"
LEAST review, August 10 & 11, 2016, University of Notre Dame20160
0
"Double Gated TMD p/n Junctions for TFET Applications"
LEAST review, August 10 & 11, 2016, University of Notre Dame20160
0
"Atomistic modeling of 2D material devices"
US-EU workshop on 2D layered materials and devices, Arlington, Virginia, April 22, 201520160
0
"Multiscale Transport Simulation of Nanoelectronic Devices with NEMO5"
Progress In Electromagnetics Research Symposium (PIERS), August, 2016, Shanghai, China20160
0
"STEEP Transistor Modeling with NEMO5"
Steep Transistors Workshop, University of Notre Dame, Notre Dame, IN, October 5-6, 201520150
0
"Tunneling: The Major Issue in Ultra-scaled MOSFETs"
IEEE Nano, Rome, Italy, July 26-30, 201520150
0
"Transport properties of bilayer graphene field effect transistor"
TECHCON 2015, Sept. 20-22, 2015, Austin, TX, United States20150
0
"Electrically Doped 2D Material Tunnel Transistors"
International Workshop on Computational Electronics (IWCE 2015) September 2, 2015 West Lafayette, Indiana USA20150
0
"Atomistic Simulation of Electrically Doped WTe2 Tunnel Transistor"
The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Washington DC, USA, September 9-11, 201520150
0
"Achieving a higher ON/OFF ratio in Bilayer Graphene FET-- Strain Engineering"
The International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Washington DC, USA, September 9-11, 201520150
0
"Transport characteristics of Nitride TFETs: Ballistic versus scattering"
2015 LEAST (Center for Low Energy Systems Technology) Annual Review, August 12 & 13, 2015 , University of Notre Dame.20150
0
"High Performance Bilayer graphene transistors"
LEAST review, student poster, South Bend, IN, Aug. 201520150
0
"Challenges and Solutions for 2D Material Tunnel Transistors"
TECHCON 2015, Sept. 20-22, 2015, Austin, TX, United States.20150
0
"Quantum Dot Lab: An Online Platform for Quantum Dot Simulations"
The Second Annual nanoHUB User Conference, Purdue University on August 31 - September 1, 201520150
0
"Quantum Dot Lab: An Online Platform for Quantum Dot Simulations"
International Workshop on Computational Electronics (IWCE 2015) September 2, 2015 West Lafayette, Indiana USA20150
0
"2D Tunnel Transistors for Ultra-Low Power Applications: Promises and Challenges"
Fourth Berkeley Symposium on Energy Efficient Electronic Systems (2015)20150
0
"Transport properties of 2D material transistors"
17th International Workshop on Computational Electronics (IWCE), Paris, France, 201420140
0
"Transport Properties of 2D Material Transistors"
TECHON 2014, October 1-3, 2014, Santa Clara, CA20140
0
"Atomistic Simulation of Steep Subthreshold Slope Bi-layer MoS2 Transistors"
Poster Session, 2014 IEEE Silicon Nanoelectronics Workshop, Hilton Hawaiian Village, Honolulu, HI USA June 8-9, 201420140
0
"Atomistic Tight-binding Modeling of III-Nitride Materials and Field Effect Transistors"
2014 LEAST (Center for Low Energy Systems Technology) Annual Review, August 12 - 14, 2014 , University of Notre Dame.20140
0
"Optimization of the Anharmonic Strain Model to Capture Realistic Strain Distributions in Quantum Dots"
IEEE Nano, Toronto, 201420140
0
"Tight Binding modeling of monolayer MoS2 and ilayer graphene devices"
2013 LEAST (Center for Low Energy Systems Technology) Annual Review, August 14 & 15, 2013 , University of Notre Dame.20130
0
"Atomistic Modeling of Nitride Devices"
2013 LEAST (Center for Low Energy Systems Technology) Annual Review, August 14 & 15, 2013 , University of Notre Dame.20130
0
"NEMO5, a Parallel, Multiscale, Multiphysics Nanoelectronics Modeling Tool"
SISPAD 2012, International Conference on Simulation of Semiconductor Processes and Devices, Denver, CO, Sept. 201220120
0