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00014 #ifndef _PIC24_SPI_H_
00015 #define _PIC24_SPI_H_
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00021
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00024
00025 #define DISABLE_SCK_PIN 0x1000
00026 #define ENABLE_SCK_PIN 0x0000
00027 #define SCK_PIN_MASK (~DISABLE_SCK_PIN)
00028
00029 #define DISABLE_SDO_PIN 0x0800
00030 #define ENABLE_SDO_PIN 0x0000
00031 #define SDO_PIN_MASK (~DISABLE_SDO_PIN)
00032
00033 #define SPI_MODE16_ON 0x0400
00034 #define SPI_MODE8_ON 0x0000
00035 #define SPI_MODE_MASK (~SPI_MODE16_ON)
00036
00037 #define SPI_SMP_ON 0x0200
00038 #define SPI_SMP_OFF 0x0000
00039 #define SPI_SMP_MASK (~SPI_SMP_ON)
00040
00041 #define SPI_CKE_ON 0x0100
00042 #define SPI_CKE_OFF 0x0000
00043 #define SPI_CKE_MASK (~SPI_CKE_ON)
00044
00045 #define SLAVE_ENABLE_ON 0x0080
00046 #define SLAVE_ENABLE_OFF 0x0000
00047 #define SLAVE_ENABLE_MASK (~SLAVE_ENABLE_ON)
00048
00049 #define CLK_POL_ACTIVE_LOW 0x0040
00050 #define CLK_POL_ACTIVE_HIGH 0x0000
00051 #define CLK_POL_ACTIVE_MASK (~CLK_POL_ACTIVE_LOW)
00052
00053 #define MASTER_ENABLE_ON 0x0020
00054 #define MASTER_ENABLE_OFF 0x0000
00055 #define MASTER_ENABLE_MASK (~MASTER_ENABLE_ON)
00056
00057 #define SEC_PRESCAL_1_1 0x001c
00058 #define SEC_PRESCAL_2_1 0x0018
00059 #define SEC_PRESCAL_3_1 0x0014
00060 #define SEC_PRESCAL_4_1 0x0010
00061 #define SEC_PRESCAL_5_1 0x000c
00062 #define SEC_PRESCAL_6_1 0x0008
00063 #define SEC_PRESCAL_7_1 0x0004
00064 #define SEC_PRESCAL_8_1 0x0000
00065 #define SEC_PRESCAL_MASK (~SEC_PRESCAL_1_1)
00066
00067 #define PRI_PRESCAL_1_1 0x0003
00068 #define PRI_PRESCAL_4_1 0x0002
00069 #define PRI_PRESCAL_16_1 0x0001
00070 #define PRI_PRESCAL_64_1 0x0000
00071 #define PRI_PRESCAL_MASK (~PRI_PRESCAL_1_1)
00072
00073
00074 #define SPI_ENABLE 0x8000
00075 #define SPI_DISABLE 0x0000
00076 #define SPI_ENBL_DSBL_MASK (~SPI_ENABLE)
00077
00078 #define SPI_IDLE_STOP 0x2000
00079 #define SPI_IDLE_CON 0x0000
00080 #define SPI_IDLE_MASK (~SPI_IDLE_STOP)
00081
00082 #define SPI_RX_OVFLOW 0x0040
00083 #define SPI_RX_OVFLOW_CLR 0x0000
00084
00085
00086 #define FRAME_ENABLE_ON 0x8000
00087 #define FRAME_ENABLE_OFF 0x0000
00088 #define FRAME_ENABLE_MASK (~FRAME_ENABLE_ON)
00089
00090 #define FRAME_SYNC_INPUT 0x4000
00091 #define FRAME_SYNC_OUTPUT 0x0000
00092 #define FRAME_SYNC_MASK (~FRAME_SYNC_INPUT)
00093
00094 #define FRAME_SYNC_ACTIVE_HIGH 0x2000
00095 #define FRAME_SYNC_ACTIVE_LOW 0x0000
00096 #define FRAME_SYNC_POL_MASK (~FRAME_SYNC_ACTIVE_HIGH)
00097
00098 #define SPI_FRM_PULSE_FIRST_CLK 0x0002
00099 #define SPI_FRM_PULSE_PREV_CLK 0x0000
00100 #define SPI_FRM_PULSE_MASK (~SPI_FRM_PULSE_FIRST_CLK)
00101
00102 #define SPI_ENH_BUFF_ENABLE 0x0001
00103 #define SPI_ENH_BUFF_DISABLE 0x0000
00104 #define SPI_ENH_BUFF_MASK (~SPI_ENH_BUFF_ENABLE)
00105
00106
00107 #if (NUM_SPI_MODS >= 1)
00108 uint16 ioMasterSPI1(uint16 u16_c);
00109 #endif
00110
00111
00112 #if (NUM_SPI_MODS >= 2)
00113 uint16 ioMasterSPI2(uint16 u16_c);
00114 #endif
00115
00116
00117 #endif