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00014 #ifndef _PIC24_DMA_H_
00015 #define _PIC24_DMA_H_
00016
00017
00018
00019 #define DMA_MODULE_ON 0x8000
00020 #define DMA_MODULE_OFF 0x0000
00021 #define DMA_MODULE_MASK (~DMA_MODULE_ON)
00022
00023 #define DMA_SIZE_BYTE 0x4000
00024 #define DMA_SIZE_WORD 0x0000
00025 #define DMA_SIZE_MASK (~DMA_SIZE_BYTE);
00026
00027 #define DMA_DIR_WRITE_PERIPHERAL 0x2000
00028 #define DMA_DIR_READ_PERIPHERAL 0x0000
00029 #define DMA_DIR_MASK (~DMA_DIR_WRITE_PERIPHERAL)
00030
00031 #define DMA_INTERRUPT_HALF 0x1000
00032 #define DMA_INTERRUPT_FULL 0x0000
00033 #define DMA_INTERRUPT_MASK (~DMA_INTERRUPT_HALF)
00034
00035 #define DMA_NULLW_ON 0x0800
00036 #define DMA_NULLW_OFF 0x0000
00037 #define DMA_NULLW_MASK (~DMA_NULLW_ON)
00038
00039 #define DMA_AMODE_PERIPHERAL_INDIRECT 0x0020
00040 #define DMA_AMODE_REGISTER_INDIRECT 0x0010
00041 #define DMA_AMODE_REGISTER_POSTINC 0x0000
00042 #define DMA_AMODE_MASK (~DMA_AMODE_PERIPHERAL_INDIRECT)
00043
00044
00045 #define DMA_MODE_ONE_SHOT_PING_PONG 0x0003
00046 #define DMA_MODE_CONTINUOUS_PING_PONG 0x0002
00047 #define DMA_MODE_ONE_SHOT 0x0001
00048 #define DMA_MODE_CONTINUOUS 0x0000
00049 #define DMA_MODE_MASK (~DMA_MODE_ONE_SHOT_PING_PONG)
00050
00051
00052 #define DMA_IRQ_INT0 0x0000
00053 #define DMA_IRQ_IC1 0x0001
00054 #define DMA_IRQ_OC1 0x0002
00055 #define DMA_IRQ_IC2 0x0005
00056 #define DMA_IRQ_OC2 0x0006
00057 #define DMA_IRQ_TMR2 0x0007
00058 #define DMA_IRQ_TMR3 0x0008
00059 #define DMA_IRQ_SPI1 0x000A
00060 #define DMA_IRQ_U1RX 0x000B
00061 #define DMA_IRQ_U1TX 0x000C
00062 #define DMA_IRQ_ADC1 0x000D
00063 #define DMA_IRQ_ADC2 0x0015
00064 #define DMA_IRQ_U2RX 0x001E
00065 #define DMA_IRQ_U2TX 0x001F
00066 #define DMA_IRQ_SPI2 0x0021
00067 #define DMA_IRQ_ECAN1RX 0x0022
00068 #define DMA_IRQ_ECAN2RX 0x0037
00069 #define DMA_IRQ_ECAN1TX 0x0046
00070 #define DMA_IRQ_ECAN2TX 0x0047
00071
00072
00073 #endif