Spin Tranfer Toque MRAM
STT-MRAM is a promising memory technology for on-chip caches because of its high density and non-volatile nature. The conventional STT-MRAM bit-cell consist of a Magnetic Tunnel Junction (MTJ) and an access transistor. In this two terminal bit-cell, the read and write currents flow through the same terminals which introduces a design conflict between the two operations. In other words, a bit-cell optimized for write can suffer from poor read performance, and vice versa. Furthermore, the access transistor needs to drive a bi-directional write current which causes a conflict between writability and tunnel barrier reliability. In order to mitigate the read/write conflict and improve the oxide reliability, several techniques have been proposed at the device, circuit and architecture levels of abstraction. At the device level, several three terminal MTJ structures have been proposed that can:
- electrically and physically decouple the read / write current paths
- use non-local spin current to write, which mitigates oxide reliability issues
- provide a unidirectional write scheme with fully-differential read
Though STT-MRAM has the advantage of zero stand-by leakage, its write energy can be higher than other on-chip memories such as SRAM and e-DRAM. In order to lower the write energy of 1T-1MTJ bit-cells, circuit techniques such as balanced-write scheme with multiple voltages, asymmetric write current paths using multiple source lines and pass transistors have been proposed. In addition to lowering the write energy, these circuit techniques simultaneously improve the reliability of the tunnel barrier. In addition, tilting the anisotropy of the free layer has also shown substantial reduction in the write energy of two and three terminal STT-MRAM bit-cells.
The micro-architecture implications of different flavors of STT-MRAM bit-cells was analyzed within the SimpleScalar and Cacti framework. Due to the non-volatility of STT-MRAM, it does not suffer from half-select problem which is common in SRAM caches. This feature of STT-MRAM has been exploited to propose techniques such as sequential cache read and partial cache line update, which further improve the energy efficiency of STT MRAM caches. Moreover, the asymmetric write latency of two terminal bit-cells can be exploited to improve the effective write latency at the cache architecture level.
- J. Li, C. Augustine, S. Salahuddin, and K. Roy, "Modeling of Failure Probability and Statistical Design of Spin-Torque Transfer Magnetic Random Access Memory (STT MRAM) Array for Yield Enhancement," ACM/IEEE Design Automation Conference, June 2008.
- J. Li, H. Liu, S. Salahuddin, and K. Roy, "Variation-Tolerant Spin-Torque Transfer (STT) MRAM Array for Yield Enhancement," IEEE Custom Integrated Circuits Conference, September 2008.
- J. Li, P. Ndai, A. Goel, and K. Roy, "An Alternate Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) from Circuit/Architecture Perspective," IEEE Asia and South Pacific Design Automation Conference, Jan. 2009.
- J. Li, P. Ndai, A. Goel, S. Salahuddin, and K. Roy, "Design Paradigm for Robust Spin-Torque Transfer Magnetic RAM (STT MRAM) from Circuit /Architecture Perspective," IEEE Transactions on VLSI Systems, 2009, Digital Object Identifier: 10.1109/TVLSI.2009.2027907. (2013 IEEE Transactions on VLSI Best paper Award).
- N. Mojumder, C. Augustine, D. Nikonov, and K. Roy, "Spin Torques Estimation and Magnetization Dynamics in Dual Barrier Resonant Tunneling Penta-Layer Magnetic Tunnel Junctions," 2010 Device Research Conference, pp. 93-94, June 21-23, 2010.
- C. Augustine, A. Raychowdhury, D. Somsekhar, J. Tschanz, K. Roy, and Vivek De, “Numerical Analysis of Typical STT-MTJ Stacks for 1T-1R Memory Arrays”, IEEE International Electron Devices Meeting (IEDM), 2010.
- N. Mojumder, C. Augustine, D. Nikonov, and K. Roy, "Electronic Transport and Effect of Quantum Confinement in Dual Barrier Resonant Tunneling Spin-Torque-Transfer Magnetic Tunnel Junctions,” Journal of Applied Physics (JAP), November 2010.
- N. Mojumder, S. Gupta, and K. Roy, "Dual Pillar Spin Transfer Torque MRAM with Tilted Magnetic Anisotropy for Fast & Error-free Switching," Device Research Conference, June, 2011.
- C. Augustine, N. Mojumder, X. Fong, H. Choday, S. Park, and K. Roy, "STT-MRAMs for future universal memories: Perspective and Prospective," 2012 28th International Conference on Microelectronics (MIEL), pp. 349 - 355, Nis, Serbia. (Invited talk)
- C. Augustine, A. Raychowdhury, B. Behin-Aein, J. Tschanz, V.K. De, and K. Roy, "Numerical Analysis of Domain Wall Propagation for Dense Memory Arrays," IEEE Electron Devices Meeting (IEDM), December 2011.
- N. Mojumder, S. Gupta, H. Choday, D. Nikonov, and K. Roy, "A Three Terminal Dual Pillar Spin-Transfer Torque (STT) MRAM for High Performance, Robust Memory Applications," IEEE Transactions on Electron Devices, pp. 1508-1516, May 2011.
- C. Augustine, A. Raychowdhury, D. Somsekhar, J. Tschanz, V. De and K. Roy, “Design Space Exploration of Typical STT MTJ Stacks in Memory Arrays in the Presence of Variability and Disturbances”, IEEE Transactions on Electron Devices (TED), December, 2011.
- X. Fong, S.H. Choday, and K. Roy, "Bit-Cell Level Optimization for Non-volatile Memories Using Magnetic Tunnel Junctions and Spin-Transfer Torque Switching," IEEE Transactions on Nanotechnology, January 2012, pp. 172-181.
- S. K. Gupta, S-P. Park, N. N. Mojumder and K. Roy, "Layout-Aware Optimization of STT MRAMs," in Proc. DATE 2012
- C. Augustine, N. N. Mojumder, X. Fong, H. Choday, S. P. Park and K. Roy, “Spin-Transfer Torque MRAMs for Low Power Memories: Prospects and Perspective”, IEEE Sensors Journal, April 2012, pp. 756-766.
- S. Park, S. Gupta, N. Mojumder, A. Raghunathan, and K. Roy, "Future Cache Design using STT MRAMs for Improved Energy Efficiency: Devices, Circuits, and Architecture," ACM/IEEE Design Automation Conference, June 2012.
- N. Mojumder, D. Abraham, K. Roy, and D. Worledge, "Magnonic spin-transfer Torque MRAM with Low Power, High Speed, and Error-free switching," IEEE Transactions on Magnetics, June 2012, pp. 2016-2025.
- M. Sharad G. Panagopoulos, C. Augustine, and K. Roy, "NLSTT-MRAM: Robust Spin Transfer Torque MRAM using Non-Local Spin Injection for Write," Device Research Conference, June 2012.
- G. Panagopoulos, C. Augustine, X. Fong, and K. Roy, "Exploring Variability and Reliability of Multi-Level STT-MRAM Cells," Device Research Conference, June 2012.
- Y. Kim, S. Gupta, S. Park, G. Panagopoulos, and K. Roy, "Write-Optimized Reliable Design of STT MRAM," ACM/IEEE International Symposium on Low Power Electronics and Design, July-August, 2012. (Best paper nomination)
- D. Lee, S. Gupta, and K. Roy, "High-Performance Low-Energy STT MRAM Based on Balanced Write Scheme," ACM/IEEE International Symposium on Low Power Electronics and Design, July-August, 2012.
- R. Venkatesan, V. Kozhikkottu, C. Augustine, A. Raychowdhury, K. Roy, and A. Raghunathan, "TapeCache: A High Density, Energy Efficient Cache Based on Domain Wall Memory," ACM/IEEE International Symposium on Low Power Electronics and Design, July-August, 2012. (Best paper award)
- N. Mojumder and K. Roy, "Proposal for Switching Current Reduction Using Reference Layer With Tilted Magnetic Anisotropy in Magnetic Tunnel Junctions for Spin-Transfer Torque (STT) MRAM," IEEE Transactions on Electron Devices, November 2012, pp. 3054-3060.
- N. Mojumder, K. Roy, and D. Abraham, "Thermoelectric Spin-Transfer Torque MRAM with Fast Bidirectional Writing Using Magnonic Current," IEEE Transactions on Magnetics, January 2013, pp. 483-488. (Cover Story)
- X. Fong, Y. Kim, S.H. Choday, and K. Roy, "Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells," IEEE Transactions on VLSI Systems, accepted for publication (DOI: 10.1109/TVLSI.2013.2239671).
- K-W. Kwon, S. H. Choday, Y. Kim, and K. Roy, "AWARE (Asymmetric Write Architecture with REdundant blocks): A High Write Speed STT-MRAM Cache Architecture," IEEE Transactions on VLSI Systems, accepted for publication.
- X. Fong and K. Roy, "Complementary Polarizers STT-MRAM (CPSTT) for On-chip Caches," IEEE Electron Device Letters vol. 34, iss. 2, pp. 232-234, Feb. 2013.
- R. Venkatesan, M. Sharad, K. Roy, A. Raghunathan, "DWM-TAPESTRI - An Energy Efficient Cache Design using Spin memory with Domain wall Shift based WritesEditRe-order section", DATE, 2013.
- M. Sharad, R. Venkatesan, A. Raghunathan and K. Roy, "Multi-Level MRAM bit Cell Using Domain Wall Magnet", DRC 2013.
- M. Sharad, R. Venkatesan, X. Fong, A. Raghunathan and K. Roy , “Energy-Efficient MRAM-Access Scheme Using Hybrid-Circuits Based on Spintronic-Sensors”, IEEE Sensors, 2013.
- M. Sharad, R. Venkatesan, A. Raghunathan and K. Roy, “Domain-Wall Shift Based Multi-Level MRAM, for High-Speed, High-Density and Energy-Efficient Caches”, ISLPED, 2013.
- M. Sharad, R. Venkatesan, X. Fong, A. Raghunathan and K. Roy, “Spin-Torque Sensors for Spin-Torque Memory”, Nanoarch, 2013.
- X. Fong and K. Roy, "Low-power robust complementary polarizer STT-MRAM (CPSTT) for on-chip caches," in Proc. of 5th IEEE Int. Memory Workshop (IMW 2013), May 2013, pp. 88-91.
- D. Lee, X. Fong, and K. Roy, "R-MRAM: A ROM-Embedded STT MRAM Cache," IEEE Electron Device Letters (EDL), 2015.
- Y. Kim, S. H. Choday, and K. Roy, "DSH-MRAM: Differential spin Hall MRAM for on-chip memories," IEEE Electron Device Letters (EDL), 2015.
- K.-W. Kwon, X. Fong, P. Wijesinghe, P. Panda, K. Roy, "High-Density and Robust STT-MRAM Array Through Device/Circuit/Architecture Interactions", IEEE TNANO, 2015.
- Y. Kim, X. Fong, K.-W. Kwon, M.-C. Chen, K. Roy, "Multilevel Spin-Orbit Torque MRAMs", IEEE TED, 2015.
- Y. Seo, X. Fong, K. Roy, "Domain Wall Coupling-Based STT-MRAM for On-Chip Cache Applications", IEEE TED, 2015.
- A. Jaiswal, X. Fong, K. Roy "Comprehensive Scaling Analysis of Current Induced Switching in Magnetic Memories Based on In-Plane and Perpendicular Anisotropies", IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2016.
- S. Sharmin, A. Jaiswal, K. Roy, "Modeling and Design Space Exploration for Bit-Cells Based on Voltage-Assisted Switching of Magnetic Tunnel Junctions", IEEE TED, 2016.