Boolean Computation

Boolean Logic Using Spins and Nano-Magnets

Research Summary

Nano-magnets connected through metal channels in a lateral spin-valve (LSV) can interact through spin-current and can facilitate unidirectional flow of information. Current-mode switching employed in LSV’s can facilitate computation like majority evaluation. Interestingly, such spin majority gates can be used to realize compact structures for logic blocks (such as compact full adders with just five magnets) that find bulky representation in CMOS circuits. All Spin Logic (ASL) gates, being magneto-metallic, can operate at ultra low terminal voltage of few millivolts. However, power consumption of such logic can be larger than CMOS implementation because of clocking and other interconnect drivers. Note, however, that ASL can be pipelined for higher performance, without insertion of extra latches. Pipelining requires the use of clocked CMOS transistors, which significantly increase the required supply-voltage. We propose a design scheme for 3-D ASL, which involves stacking of multiple ASL layers that are clocked using the same supply gating transistor. Stacking of N ASL layers using the proposed scheme can enhance the power saving as well as area density by factor of N. In such a design, computing information can flow in spin-mode across and in-between horizontal ASL layers, while supply-current is routed along vertical vias. Use of graphene nano-ribbons that possess long diffusion length can facilitate long distance propagation of data along horizontal ASL layers in such a 3-D system. The proposed design scheme for pipelined, 3-D ASL can achieve more than two order of magnitude higher density and lower power consumption as compared to 15nm CMOS design. Further reduction in power-consumption might be possible through material, device (both ASL as well as clocking transistor) and circuit-level optimizations.

Synthesis methodologies for ASL based on majority logic are under exploration.

Publications

1. C. Augustine, B. Behin-Aein, and K. Roy, "Nano-Magnet Based Ultra-Low Power Logic Design Using Non-Majority Gates," IEEE NANO, July 2009, Genoa, Italy.
2. Y. Gao, C. Augustine, D. E. Nikonov, K. Roy and M. Lundstrom, “Realistic Spin-FET Performance Assessment for Reconfigurable Logic Circuits”, IEEE VLSI Technology Symposium, 2010.
3. C. Augustine, X. Fong, B. Behin-Aein, K. Roy, “Ultra-low Power Nano-magnet Based Computing: A System-Level Perspective,” IEEE Transactions on Nanotechnology, July 2011, pp. 778-788.
4. M. Sharad, C. Augustine, and K. Roy, "Boolean and Non-Boolean Computing with Spin Devices," International Electron Devices Meeting (IEDM), December 2012.
5. M. Sharad, K. Yogendra, K. Kwon, and K. Roy, "Design Of Ultra High Density And Low Power Computational Blocks Using Nano-Magnets," IEEE International Symposium on Quality of Electronic Design (ISQED), March 2013.
6. M. Sharad and K. Roy. "Spintronic Switches for Ultra Low Energy On-Chip and Inter-Chip Current-Mode Interconnects." Electron Device Letter, 2013.
7. M. Sharad and K. Roy, “"Ultra-low Energy Global Interconnects based on Spin Torque Switches", IEDM, 2013
8. M. Sharad  and K. Roy, “Modelling and Simulation Based Study of Spintronic Switches for Ultra Low Energy Global Interconnects", Journal of App. Phys., 2013 (accepted)
9. M. Sharad, K. Yogendra, Arun Gaud, Kon-Woo Kwon and K. Roy, “Ultra-High Density, High-Performance and Energy-Efficient All Spin Logic”, IEEE Transaction on Nanotechnology,2013
10. M. Sharad, D. Fan, K. Roy, "Ultra-low Energy, High-Performance Dynamic Resistive Threshold Logic" TNANO letters, 2013
11. M. Sharad, D. Fan, K. Roy, "Ultra-low Energy Programmable Magnetic Threshold Logic" IEEE Magnetic Letters, 2013
12. M. Sharad, D. Fan, K. Yogendra, K. Roy, “Programmable and Fixed Boolean Logic Using Spin  Torque Devices”, Berkeley Symposium on Energy Efficient Electronic Systems, 2013
13. D. Fan, M. Sharad, K. Roy, "Design and Synthesis of Ultra Low Energy Spin-Memristor Threshold Logic", IEEE Transaction on Nanotechnology,2014
14. Z. Pajouhi, S. Venkataramani, K. Yogendra, A. Raghunathan, K. Roy, "Exploring Spin-Transfer-Torque Devices for Logic Applications", IEEE TCAD, 2015.
15. M.-C. Chen, Y. Kim, K. Yogendra, K. Roy, "Domino-Style Spin–Orbit Torque-Based Spin Logic", IEEE Magnetic Letters, 2015.