Research: AI Hardware

AI Hardware

Our research focuses on developing specialized systems that efficiently support the growing demands of artificial intelligence workloads. As AI algorithms become more complex and data-intensive, we recognize the challenges that traditional hardware architectures face in terms of performance, power consumption, and scalability. To address these limitations, we explore innovative hardware approaches and technologies that make AI processing faster, more efficient, and secure. Our work spans across Compute-In-Memory and Compute-Near-Memory architectures, neuromimetic devices, co-design, AI-driven secure hardware, and AI for hardware design, each contributing to the next generation of AI systems.

D. Hardware for Combinatorial Optimization

Our research in hardware for combinatorial optimization focuses on domain-specific architectural and device-innovations to solve computationally intensive, NP-hard problems efficiently. By leveraging emerging non-volatile memory technologies such as MRAMs and compute-in-memory primitives, we develop acceleration frameworks and in-memory annealing architectures. Through cross-layer co-design combining hierarchical algorithmic strategies with crossbar-based Ising macros, our work enables energy-efficient, scalable optimization solvers suited for routing applications.

Publications:

1. Holla, Amod, Sumedh Chatterjee, Sutanu Sen, Anushka Mukherjee, Fernando Garcia-Redondo, Dwaipayan Biswas, Francesca Iacopi, and Kaushik Roy. "LIMO: Low-power in-memory-annealer and matrix-multiplication primitive for edge computing." npj Unconventional Computing, 2026.

   Abstract: Combinatorial optimization (CO) underpins critical applications in science and engineering, ranging from logistics to electronic design automation. A classic example of CO is the NP-complete Traveling Salesman Problem (TSP). Finding exact solutions for large-scale TSP instances remains computationally intractable; on von Neumann architectures, such solvers are constrained by the memory wall, incurring compute-memory traffic that grows with instance size. Metaheuristics, such as simulated annealing implemented on compute-in-memory (CiM) architectures, offer a way to mitigate the von Neumann bottleneck. This is accomplished by performing in-memory optimization cycles to rapidly find approximate solutions for TSP instances. Yet this approach suffers from degrading solution quality as instance size increases, owing to inefficient state-space exploration. To address this, we present LIMO, a programmable mixed-signal computational macro that implements an in-memory annealing algorithm with reduced search-space complexity. The annealing process is aided by the stochastic switching of spin-transfer-torque magnetic-tunnel-junctions (STT-MTJs) to escape local minima. For large instances, our macro co-design is complemented by a refinement-based divide-and-conquer algorithm amenable to parallel optimization in a spatial architecture. Consequently, our system comprising several LIMO macros achieves superior solution quality and faster time-to-solution on instances up to 85,900 cities compared to prior hardware annealers. The modularity of our annealing peripherals allows the LIMO macro to be reused for other applications, such as vector-matrix multiplications (VMMs). This enables our architecture to support neural network inference. As an illustration, we show image classification and face detection with software-comparable accuracy, while achieving lower latency and energy consumption than baseline CiM architectures.

2. Yoo, Sangmin, Amod Holla, Sourav Sanyal, Dong Eun Kim, Francesca Iacopi, Dwaipayan Biswas, James Myers, and Kaushik Roy. "TAXI: Traveling Salesman Problem Accelerator with X-bar-based Ising Macros Powered by SOT-MRAMs and Hierarchical Clustering." ACM/IEEE Design Automation Conference (DAC), 2025.

   Abstract: Ising solvers with hierarchical clustering have shown promise for large-scale Traveling Salesman Problems (TSPs), in terms of latency and energy. However, most of these methods still face unacceptable quality degradation as the problem size increases beyond a certain extent. Additionally, their hardwareagnostic adoptions limit their ability to fully exploit available hardware resources. In this work, we introduce TAXI ? an inmemory computing-based TSP accelerator with crossbar(Xbar)-based Ising macros. Each macro independently solves a TSP subproblem, obtained by hierarchical clustering, without the need for any off-macro data movement, leading to massive parallelism. Within the macro, Spin-Orbit-Torque (SOT) devices serve as compact energy-efficient random number generators enabling rapid ?natural annealing?. By leveraging hardware-algorithm co-design, TAXI offers improvements in solution quality, speed, and energy-efficiency on TSPs up to 85,900 cities (the largest TSPLIB instance). TAXI produces solutions that are only 22% and 20% longer than the Concorde solver?s exact solution on 33,810 and 85,900 city TSPs, respectively. TAXI outperforms a current state-of-the-art clustering-based Ising solver, being 8× faster on average across 20 benchmark problems from TSPLib.

Click on the expansion arrows in each section to read the publication abstracts.