Research: AI Hardware

AI Hardware

Our research focuses on developing specialized systems that efficiently support the growing demands of artificial intelligence workloads. As AI algorithms become more complex and data-intensive, we recognize the challenges that traditional hardware architectures face in terms of performance, power consumption, and scalability. To address these limitations, we explore innovative hardware approaches and technologies that make AI processing faster, more efficient, and secure. Our work spans across Compute-In-Memory and Compute-Near-Memory architectures, neuromimetic devices, co-design, AI-driven secure hardware, and AI for hardware design, each contributing to the next generation of AI systems.

E. AI for Hardware Design

Our research focuses on developing agentic frameworks to automate complex electronic design workflows. By coupling Large Language Models (LLMs) with specialized EDA tools, these frameworks can interpret design goals, plan and execute multi-step tasks, and analyze tool feedback. This closed-loop approach enables iterative refinement of design solutions. Our goal is to develop reliable systems that accelerate design iteration and exploration while reducing manual engineering effort.

Publications:

1. Mukherjee, Anushka, Kang He, and Kaushik Roy. "DRC-Aid: Design-Rule Correction via Agentic Framework utilizing Inference-Time Large Language Models." arXiv, 2026.

   Abstract: Resolving Design Rule Violations (DRVs) in layouts entails an iterative loop of geometric edits and verification. We present DRC-Aid, a closed-loop agentic framework that automates local DRC repair by formulating it as verification-in-the-loop search. To constrain the combinatorial geometric repair space, a deterministic Rule Engine converts physical verification tool-reported violations into a bounded menu of geometric edits. An off-the-shelf Large Language Model (LLM) evaluates local geometric context to select edits from this menu, with budgeted depth-first search and backtracking. Immediate feedback from verification tools such as Calibre nmDRC/nmLVS enforces geometric compliance and guards against electrical-topology degradation, while a global Memory Bank prevents cyclic re-exploration. Evaluated on FreePDK45 layouts containing DRVs, DRC-Aid achieves DRC-clean, LVS-equivalent repairs in ~92.5% of cases with a ~98% total violation reduction, while residual cases yield partially repaired LVS-equivalent candidates. Under an identical search and verification infrastructure, LLM-based selection outperforms random (54.4%) and deterministic-heuristic (83.3%) policies, with the gap widening on cases with six or more violations.

2. Chandra, Soumyadeep, Sayeed Shafayet Chowdhury, and Kaushik Roy. "2D-ThermAl: Physics-Informed Framework for Thermal Analysis of Circuits using Generative AI." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2025). CODE AVAILABLE HERE

   Abstract: Thermal analysis is increasingly critical in modern integrated circuits, where non-uniform power dissipation and high transistor densities can cause rapid temperature spikes and reliability concerns. Traditional methods, such as FEM-based simulations, offer high accuracy but are computationally prohibitive for early-stage design, often requiring multiple iterative redesign cycles to resolve late-stage thermal failures. To address these challenges, we propose '2D-ThermAl', a physics-informed generative AI framework that effectively identifies heat sources and estimates full-chip transient and steady-state thermal distributions directly from input activity profiles. ThermAl employs a hybrid U-Net architecture enhanced with positional encoding and a Boltzmann regularizer to maintain physical fidelity. Our model is trained on an extensive dataset of heat dissipation maps for over 200 circuit configurations, ranging from simple logic gates (e.g., inverters, NAND, XOR) to complex designs, generated using COMSOL and Cadence EDA flows. The dataset captures diverse activity patterns, and we note that material-dependent thermal properties may require targeted fine-tuning to ensure accuracy across different fabrication contexts. Experimental results demonstrate that 2D-ThermAl provides precise temperature mappings for large circuits, with a root mean squared error (RMSE) of only 0.71°C and outperforms conventional FEM tools by running up to ∼ 200× faster. We analyze performance across diverse layouts and workloads and discuss its applicability to large-scale EDA workflows. Although thermal reliability assessments often extend beyond 85°C for post-layout signoff, our focus here is on early-stage hotspot detection and thermal pattern learning. To ensure generalization beyond the nominal operating range (25-55°C), we additionally performed cross-validation on an extended dataset that spans 25-95°C, maintaining a high accuracy (< 2.2% full-scale RMSE) even under elevated temperature conditions representative of the peak power and stress scenarios. Limitations such as 2D-only modeling and real-world validation are addressed with concrete future directions, including 3D extension, generalization across technology nodes, and transfer learning strategies.

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