[BNC-grads-list] Thesis presentation on Tuesday (04/20) @12:00pm in BRK 2001

[Ehtesham Islam]

Dear All,

I will be taking my Ph.D. Final Exam on Tuesday (04/20) at 12:00pm in BRK
2001. Hope to see you all there during the presentation. The title and the
abstract of my thesis is provided below. 

Thanks. 

- Ehtesham


Title: Theory and Characterization of Random Defect Formation and its
Implication in Variability of Nanoscale Transistors

Abstract:
Over the last 50 years, carrier transport has been the central research
topic in the semiconductor area. The outcome was a dramatic improvement in
the performance of transistor, which is one of the basic building blocks in
almost all the modern electronic devices. However, nanoscale dimension of
current transistors following Moore's law have shifted the spotlight from
carrier transport towards the reliability and variability constraints.
Modern transistors operate with high electric field. They also use small
metal gates and high- κ gate dielectric. Therefore, these transistors
regularly suffer from process variations due to statistical variation in
metal grain orientations at the gate, number of dopants in the substrate,
thickness of the dielectric, etc. In addition to these 'time-zero' variation
sources, presence of high oxide electric field and use of high-κ materials
as dielectric (like silicon oxynitride and hafnium-based materials) strains
the chemical bonds in the bulk and interface of the amorphous dielectric. As
a result, defects are formed within the transistor, which leads to
'time-dependent' variation. Taken together, these 'time-zero' and
'time-dependent' phenomenon cause variation in transistor parameters (e.g.,
threshold voltage, mobility, sub-threshold slope, drain current) - which
eventually lead to IC failure, when the variation goes beyond certain
pre-defined limit. 

In this thesis, a physical model is developed to understand the defect
formation at the dielectric/substrate interface of a transistor (a
phenomenon, generally known as Negative Bias Temperature Instability), which
is one of the major scaling concerns in current transistors. The time
dynamics of interface defect generation is captured within a
Reaction-Diffusion framework and hence compared with characteristic
experimental signatures measured over a wide range of supply voltage,
temperature, materials within the dielectric, and channel strain. This
comprehensive analysis further establishes the subtleties in interface
defect characterization using modern techniques and also explains the
intricacies for analyzing the impact of defect generation in circuit level.
More importantly, the study with interface defects has identified the
presence of self-compensation in advanced CMOS technology. And such
self-compensation is shown to be generally applicable for many sources of
'time-dependent' and 'time-zero' variabilities. Design of such
variation-resilient transistor may reshape how circuits are designed and
evaluated currently for handling process-induced (time-zero) and temporal
(time-dependent) variations - which is one of the grand challenges for
continuing transistor scaling following Moore's law.

------------------------
Ahmad Ehteshamul Islam
PhD Candidate
ECE, Purdue University
http://web.ics.purdue.edu/~aeislam