[Bnc-faculty-all-list] Seminar by Prof. Anand Bulusu (IIT Roorkee) on March 22

[Gupta, Sumeet Kumar]

Resending with additional Zoom meeting information (sorry to spam your inboxes)


Improving performance by considering the device level phenomena at circuit level abstraction


Prof. Anand Bulusu

Indian Institute of Technology Roorkee

Tuesday, March 22, 2022: 2 PM-3 PM • MSEE 239


Zoom link:  https://purdue-edu.zoom.us/j/91236098799?pwd=<https://purdue-edu.zoom.us/j/91236098799?pwd=TmFrRXkrS3B1TlpyekM1T2E0NDl5QT09>TmFrRXkrS3B1TlpyekM1T2E0NDl5QT09<https://purdue-edu.zoom.us/j/91236098799?pwd=TmFrRXkrS3B1TlpyekM1T2E0NDl5QT09>


Meeting ID: 912 3609 8799

Passcode: 874964
One tap mobile
+13462487799,,91236098799#,,,,*874964# US (Houston)
+16465588656,,91236098799#,,,,*874964# US (New York)

Dial by your location
        +1 346 248 7799 US (Houston)
        +1 646 558 8656 US (New York)
        +1 669 900 6833 US (San Jose)
        +1 253 215 8782 US (Tacoma)
        +1 301 715 8592 US (Washington DC)
        +1 312 626 6799 US (Chicago)
Meeting ID: 912 3609 8799
Passcode: 874964
Find your local number: https://purdue-edu.zoom.us/u/aeop4YN2z6




Abstract

Our work is mainly towards linking VLSI device level phenomena to circuit performance for developing systematic circuit design methods. We develop models and use them to systematically design digital and analog circuits considering PVT, layout dependent and temporal variations in near/sub-threshold and nominal voltage regimes. We also improve the digital/analog circuit performance in multi-gate CMOS technologies considering the significant gate control of the carrier densities in their device drain/source extension regions. In this talk, we mainly describe our work in understanding the physics of dielectric (DE) phase and FE layer/interface traps in NC/FeFET devices and their impact on circuit reliability. We also discuss the impact of polarization asymmetry in the FE layer due to drain-source voltage in NC/FeFETs. We discuss that the presence of DE phase causes non-uniformity in the polarization (PFE) and potential (VFE) inside the FE-layer in the gate-dielectric stack. With a higher FE thickness (TFE) and a higher DE phase, PFE becomes direction-dependent. The randomly varying DE phase, therefore, introduces the higher reliability concerns for NC-FETs. In FeFETs, we observe and explain that there exists a certain DE percentage threshold below which the increase of the DE phase does not significantly impact the device memory window. Increasing the DE phase increases the variation in the memory window. We observe that another reliability issue in NCFETs is caused by the interface Si–SiO2 and SiO2–HfO2 or bulk HfO2 traps, which change the FE polarization. The FE layer polarization asymmetry due to drain-source voltage also gives rise to important effects in NC circuits such as the negative differential resistance (NDR) to positive differential resistance (PDR) transition. The NDR-to-PDR transition occurs because the FE layer capacitance changes from a negative to positive state during channel pinch-off. This, in turn, results in a valley point in the output characteristic (IDS–VDS) at which the output resistance is infinite. The valley point can be altered using body bias in an FDSOI-NCFET device, which we used in designing simple analog building blocks. To mitigate the NDR effect and obtain a nearly zero (but positive) gds, we also propose a BOX engineered NC FDSOI FET, with the buried oxide (BOX) layer is subdivided into the ferroelectric (FE) layer and the SiO2 layer.


Bio

Anand Bulusu received the Ph.D. degree from Indian Institute of Technology Bombay, Mumbai, India, in 2006. He is currently a Professor with the Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee. His current research interests include circuit-device interaction, circuit performance models for resilient/robust circuit design and device physics. He worked in Freescale Semiconductor India Pvt. Ltd. (presently NXP Semiconductors) from 2007 – 2008, where he worked in the area of impact of device model parameter changes on circuit performance.


Host
Sumeet Kumar Gupta, guptask at purdue.edu, 765 494 3484


Sumeet Kumar Gupta, Ph.D.
Elmore Associate Professor
Elmore Family School of Electrical and Computer Engineering
Purdue University
465 Northwestern Ave
West Lafayette IN 47906
Phone: 765 494 3484 (o)
Email: guptask at purdue.edu
Website: https://engineering.purdue.edu/ICDL
________________________________
From: Gupta, Sumeet Kumar <guptask at purdue.edu>
Sent: Monday, March 21, 2022 5:42 AM
To: ecefaculty at ecn.purdue.edu <ecefaculty at ecn.purdue.edu>; ecepostdocs-list at ecn.purdue.edu <ecepostdocs-list at ecn.purdue.edu>; BNC-EngStaff <BNC-EngStaff at groups.purdue.edu>; bnc-faculty-all-list at ecn.purdue.edu <bnc-faculty-all-list at ecn.purdue.edu>; ecegradonline-list at ecn.purdue.edu <ecegradonline-list at ecn.purdue.edu>; ecegradstudent-list at ecn.purdue.edu <ecegradstudent-list at ecn.purdue.edu>
Subject: Seminar by Prof. Anand Bulusu (IIT Roorkee) on March 22

[cid:166a971f-70e5-4a63-bad1-f6f4cf2a04ba]

Sumeet Kumar Gupta, Ph.D.
Elmore Associate Professor
Elmore Family School of Electrical and Computer Engineering
Purdue University
465 Northwestern Ave
West Lafayette IN 47906
Phone: 765 494 3484 (o)
Email: guptask at purdue.edu
Website: https://engineering.purdue.edu/ICDL
-------------- next part --------------
An HTML attachment was scrubbed...
URL: </ECN/mailman/archives/bnc-faculty-all-list/attachments/20220321/f5bb5a35/attachment-0001.htm>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: image.png
Type: image/png
Size: 176982 bytes
Desc: image.png
URL: </ECN/mailman/archives/bnc-faculty-all-list/attachments/20220321/f5bb5a35/attachment-0001.png>