Selected Publications (Power Conscious Design)

• K. Roy and S. Prasad, ``Circuit Activity Based CMOS Logic Synthesis for for Low Power Reliable Operations,'' IEEE Transactions on VLSI Systems, December, 1993, pp. 503-513.
• K. Roy and S. Prasad, ``Logic Synthesis for Reliability -- An Early Start to Controlling Electromigration and Hot Carrier Effects,'' IEEE Transactions on Reliability, June, 1995, pp. 251-255.
• T.-L. Chou and K. Roy, ``Estimation of Activity for Static and Domino CMOS Circuits Considering Signal Correlations and Simultaneous Switching,'' IEEE Transactions on Computer-Aided Design of Integrated Circuits, October 1996, pp. 1257-1265.
• K. Roy and A. Chatterjee, ``Low-Power VLSI Design,'' IEEE Design and Test of Computers, December 1994, pp. 6-7.
• Y. Ye and K. Roy, ``Energy Recovery Circuits Using Reversible and Partially Reversible Logic,'' IEEE Transactions on Circuits and Systems I, to appear in September 1996.
• D. Somasekhar and K. Roy, ``Differential Current Switch Logic: A Low-Power DCVS Logic Family,'' IEEE Journal of Solid State Circuits, pp. 981-991.
• S. Prasad and K. Roy, ``Circuit Optimization for Transistor Reordering for Minimization of Power Consumption under Delay Constraints,'' ACM Transactions on Design Automation of Electronic Systems, Vol. 1, No. 2, April 1996.
• T.-L. Chou and K. Roy, ``Accurate Estimation of Power Dissipation in CMOS Sequential Circuits,'' IEEE Trans. on VLSI Systems, September 1996, pp. 369-380.
• N. Sankarayya, K. Roy, and D. Bhattacharya, ``Algorithms for Low Power High Speed FIR Filter Realization Using Differntial Coefficients,'' IEEE Transactions on Circuits and Systems: Analog and Digital Signal Processing, June 1997, pp. 488-497. for publication.
• M. Johnson and K. Roy, ``Datapath Scheduling with Multiple Supply Voltages and Voltage Converters,'' ACM Transactions on Design Automation of Electronic Systems, July 1997.
• T.-L. Chou and K. Roy, ``Statistical Estimation of Digital Circuit Activity Considering Uncertainty of Gate Delays,'' IEICE (Japan) Transactions on Fundamentals of Electronics, Communications and Computer Sciences, special issue on VLSI Design and CAD Algorithms, accepted for publication.
• C.-Y. Wang and K. Roy, ``Maximum Power Estimation for CMOS Circuits Using Deterministic and Statistical Techniques,'' IEEE Transactions on VLSI Systems, March 1998, pp. 134-140.
• K. Roy, "Power Dissipation Driven FPGA Place and Route under Timing Constraints," IEEE Trans. on Circuits and Systems I, to appear.
• Z. Chen, K. Roy, and T.-L. Chou, ``Efficient Statistical Approach to Estimate Power Considering Uncertain Properties of Primary Inputs,'' IEEE Transactions on VLSI Systems, accepted for publication.
• C. Wang and K. Roy, ``Control Unit Synthesis Targeting Low-Power Processors,'' IEEE Transactions on VLSI Systems, accepted for publication.
• T.-L. Chou and K. Roy, ``Power Estimation Under Uncertain Delays,'' Integrated Computer-Aided Engineering, Wiley-Interscience, accepted for publication.
• K. Roy and S. Prasad, ``SYCLOP: Synthesis of CMOS Logic for Low Power Applications,'' IEEE International Conference on Computer Design, 1992, pp. 464-467.
• S. Prasad and K. Roy, "Circuit Activity Driven Multilevel Logic Optimization for Low Power Reliable Operations," European Design Automation Conference, 1993, 368-372.
• S. Datta, S. Nag, and K. Roy, "ASAP: A Transistor Sizing Tool for Speed Area and Power Optimization of Static CMOS Circuits," International Symposium on Circuits and Systems, 1994.
• S. Prasad and K. Roy, ``Circuit Optimization for Low Power Under Delay Constraints,'' International Workshop on Low Power Design, April 1994.
• K. Roy and S. Prasad, ``Power Dissipation Driven FPGA Place and Route under Delay Constraints,'' FPL-94 and in Lecture Notes in Computer Science, Springer-Verlag, 1994.
• K. Roy and S. Prasad, ``Logic Synthesis for Reliability -- An Early Start to Controlling Electromigration and Hot Carrier Effects,'' IEEE/ACM European Design Automation Conference, September 1994.
• T-L. Chou, K. Roy, and S. Prasad, ``Estimation of Circuit Activity Considering Signal Correlations and Simultaneous Switching,'' IEEE International Conference on Computer-Aided Design, November 1994, pp. 300-303.
• S. Prasad and K. Roy, ``Circuit Optimization for Transistor Reordering for Minimization of Power Consumption under Delay Constraints,'' IEEE International Conference on VLSI Design, January 1995, pp. 305-309.
• C.-Y. Wang and K. Roy, ``Control Unit Synthesis Targeting Low-Power Processors,'' IEEE International Conference on Computer Design, Austin, October 1995.
• T.-L. Chou and K. Roy, ``Accurate Estimation of Power Dissipation in CMOS Sequential Circuits,'' IEEE ASIC Conference, Austin, September 1995.
• T.-L. Chou and K. Roy, ``Estimation of Sequential Circuit Activity Considering Spatial and Temporal Correlations,'' IEEE International Conference on Computer Design, Austin, October 1995.
• Y. Ye and K. Roy ``Ultra Low Power Circuit Design using Adiabatic Switching Principle,'' IEEE Midwest Symposium on Circuits and Systems, 1995.
• D. Somasekhar and K. Roy, ``Differential Current Switch Logic: A Low Power DCVS Family,'' 21st European Solid-State Circuits Conference, 1995.
• C.-Y. Wang and K. Roy, ``Maximum Current Estimation in CMOS Circuits Using Deterministic and Statistical Techniques,'' IEEE VLSI Design Conference, Jan. 1996.
• T.-L. Chou and K. Roy, ``Statistical Estimation of Sequential Circuit Activity," IEEE/ACM International Conference on Computer-Aided Design, November 1995.
• D. Somasekhar, Y. Ye, and K. Roy, ``An Energy Recovery Static RAM Memory Core,'' IEEE Symposium on Low Power Electronics, San Jose, October 1995.
• C.-Y. Wang, T.-L. Chou, and K. Roy, ``Maximum Power Estimation Under Arbitrary Delay Model,'' IEEE International Symposium on Circuits and Systems, 1996.
• C.-Y. Wang and K. Roy, ``Maximum Power Estimation for Sequential Circuits Using a Test Generation Based Technique,'' IEEE Custom Integrated Circuits Conference, 1996.
• M. Johnson and K. Roy, ``Low-Power Datapath Scheduling under Resource Constraints,'' IEEE Intl. Conf. on Computer Design, October 1996.
• P. Patil, T.-L. Chou, K. Roy, and R. Roy, ``Low-Power Driven Logic Synthesis Using Accurate Power Estimation Technique,'' IEEE VLSI Design Conference, January 1997, pp. 179-183.
• N. Sankarayya, K. Roy, and D. Bhattacharya, ``Algorithms for Low Power FIR Filter Realization using Differential Coefficients,'' IEEE VLSI Design Conference, January 1997, pp. 174-178.
• T.-L. Chou, K. Roy, and R. K. Roy, ``Statistical Estimation of Combinational and Sequential CMOS Digital Circuit Activity Considering Uncertainty of Gate Delays,'' 1997 Asia \& South Pacific Design Automation Conference - ASP-DAC.
• K. Roy and R. Roy, "Low-Power Design: Estimation and Synthesis Techniques," tutorial presentation at 1997 Asia \& South Pacific Design Automation Conference - ASP-DAC.
• M. Johnson and K. Roy, ``Scheduling and Optimal Voltage Selection for Low Power Multi-Voltage DSP Datapaths,'' IEEE International Symposium on Circuits and Systems, Hongkong, May 1997, to appear.
• Z. Chen, K. Roy, and T.-L. Chou, ``Sensitivity of Power Dissipation to Uncertainties in Primary Input Specification,'' IEEE Custom Integrated Circuits Conference, 1997, pp. 487-490.
• K. Muhammad and K. Roy, ``Low Power Digital Filters Based on Constrained Least Squares Solution,'' 31st Asilomar Conference on Signals, Systems, and Computers, 1997, invited paper.
• Y. Ye and K. Roy, ``Reversible and Quasi Static Adiabatic Logic," European Conference on Circuit Theory and Design, 1997.
• K. Mohammed and K. Roy, ``On Power Reduction of FIR Digital Filters Using Constrained Least Square Solutions,'' IEEE International Conference on Computer Design, 1997.
• C.-Y. Wang and K. Roy, ``An ATG-Based Maximum Power Estimation Technique Considering Spurious Transitions,'' IEEE International Conference on Computer Design, 1997.
• D. Somasekhar and K. Roy, ``LVDCSL: Low Voltage Differential Current Switch Logic, A Robust Low Power DCSL Family,'' 1997 International Symposium on Low Power Electronics and Design.
• Y. Ye, K. Roy, and G. Stamoulis, ``Quasi-Static Energy Recovery Logic and Supply Clock Generation Circuits,'' 1997 International Symposium on Low Power Electronics and Design.
• R. Roy, K. Roy, and A. Chatterjee, ``Stress Testing: A Low-Cost Alternative for Burn-in,'' VLSI'97, Brazil.
• Z. Chen and K. Roy, ``An Efficient Statistical Method to Estimate Average Power in Sequential Circuits Considering Input Uncertainties,'' IEEE International ASIC Conference, Portland, 1997.
• A. Keshavarzi, K. Roy, and C. Hawkins, ``Intrinsic $I_{DDQ}$: Origins, Reduction, and Applications in Deep Sub-$\mu$ Low-Power CMOS IC's,'' IEEE International Test Conference, 1997.
• C.-Y. Wang and K. Roy, ``COSMOS: A Continuous Optimization Approach for Maximum Power Estimation of CMOS Circuits,'' ACM/IEEE International Conference on Computer-Aided Design, 1997.
• Z. Chen, K. Roy, and T.-L. Chou, ``Power Sensitivity -- A New Method to Estimate Power Considering Uncertain Specifications of Primary Inputs,'' ACM/IEEE International Conference on Computer-Aided Design, 1997.
• N. Sankarayya, K. Roy, and D. Bhattacharya, ``Optimizing Computations for Reducing Energy Dissipation in Realization of High Speed LTI-FIR Systems,'' ACM/IEEE International Conference on Computer-Aided Design, 1997.
• Y. Ye, K. Roy, and R. Drechsler, ``On Power Dissipation in AND-XOR Circuits,'' Workshop on Reed-Muller Circuits, 1997.
• L. Wei, Z. Chen, and K. Roy, ``Double Gate Dynamic Threshold Voltage (DGDT) SOI MOSFETs for Low Power High Performance Designs,'' IEEE SOI Conference, 1997.
• Z. Chen, K. Roy, and Y. Ye, ``Estimation of Average Switching Power Under Accurate Modeling of Signal Correlations,'' IEEE Custom Integrated Circuits Conference, 1998.
• L. Wei, Z. Chen, and K. Roy, ``Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits,''IEEE/ACM Design Automation Conference, 1998.
• Z. Chen and K. Roy, ``A Novel Power Macromodeling Technique Based on Power Sensitivity,'' IEEE/ACM Design Automation Conference, 1998.