Selected Publications (FPGAs)
- K. Roy, ``A Bounded Search Algorithm for Segmented Channel Routing for
FPGAs and Associated Channel Architecture Issues,''
IEEE Transactions on Computer-Aided-Design of Integrated
Circuits, November, 1993, pp. 1695-1705.
- K. Roy and S. Nag, ``On Routability for FPGA's under Faulty Conditions,'' IEEE
Transactions on Computers, to appear in Nov. 1995.
- K. Roy and S. Nag, ``Automatic Synthesis of FPGA Channel Architecture
for Performance and Routability,'' IEEE Transactions on
VLSI Systems, December 1994, pp. 508-511.
- S. Nag and K. Roy, "Performance and Routability Driven Layout for FPGAs,"
Journal of VLSI Design, to appear.
- K. Roy, "Power Dissipation Driven FPGA Place and Route under Timing Constraints,"
IEEE Trans. on Circuits and Systems I, to appear.
- K. Roy, ``Power Dissipation Driven Place and Route Under Timing Constraints,''
IEEE Transactions on Circuits and Systems I, to appear.
- K. Roy, "On Fault Modeling and Fault Tolerance of Antifuse Based FPGAs,"
IEEE Symposium on Circuits and Systems, 1993, pp. 1623-1626.
- K. Roy and M. Mehendale, ``Optimization of Channel Segmentation for
Channelled Architecture FPGAs,'' IEEE Custom Integrated Circuits
Conference, 1992, pp. 4.4.1-4.4.4.
- C. Shaw, K. Roy et. al., ``An FPGA Architecture Evaluation Framework,''
FPGA-92 workshop, Berkeley, February 1992, pp. 15-20.
- M. Mehendale and K. Roy, "Estimating Area Efficiency of Antifuse based
Channelled FPGA Architectures,"
IEEE International Conference on VLSI Design, 1993, pp. 100-103.
- S. Nag and K. Roy, "Iterative Performance and Wirability Improvement
for FPGAs," IEEE/ACM Design Automation Conference, 1993, pp. 321-325.
- K. Roy, S. Nag, and S. Dutta, "Channel Architecture Optimization
for Routability and Performance for Row-Based FPGAs,"
IEEE International Conference on Computer Design, 1993, pp. 220-223.
- K. Roy and S. Prasad, ``Power Dissipation Driven FPGA Place and Route under Delay
Constraints,'' FPL-94 and in Lecture Notes in Computer Science,
Springer-Verlag, 1994.
- K. Roy and S. Nag, ``On Channel Architecture and Routability for FPGA's
under Faulty Conditions,'' FPL-94 and in Lecture Notes in Computer Science,
Springer-Verlag, 1994.
- J. Anderson, S. Seth, and K. Roy, ``A Coarse-Grained FPGA Architecture for
High-Performance FIR Filtering,'' Sixth International Symposium on Field
Programmable Gate Arrays, 1998, Monterrey.
Kaushik Roy, kaushik@ecn.purdue.edu