EE695K Modeling and Optimization of High Performance Interconnects
Course Description
This course provides an in-depth coverage of the modeling and
optimization techniques for high-performance interconnect designs. Topics
include detailed discussions of various interconnect and device modeling
techniques in deep submicron IC designs. The course also provides a thorough
coverage of existing techniques for interconnect optimization, such as
timing-driven placement, interconnect topology optimization, optimal buffer
insertion, optimal wire-sizing, and simultaneous device and wire sizing
optimization, and clock network design for high-performance systems.
Required text/Reference material
- C.-K. Cheng, J. Lillis, S. Lin, N. Chang, Interconnect Analysis
and Synthesis, Wiley Inter-Science.
- H. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley,
1990.
Cong et al., Performance Optimization of VLSI Interconnect Layout,
Integration, the VLSI Journal 21 (1996) 1--94.
- Selected research papers from TCAD, TVLSI, and major CAD conferences
such as DAC and ICCAD
Outline
- Introduction: Trends of VLSI Interconnect, Challenges of
Interconnect Design, Overview
- Interconnect Modeling: Interconnect as R(L)C Tree, Elmore
Delay Model, Moment Computation, Asymptotic Waveform
Evaluation, Pade Via Lanczos, Pole Analysis, Transmission
Line, Signal Integrity Modeling
- Delay Calculation: Driver Modeling, RC Delay Calculation
- Timing-Driven Placement: Delay budgetting, Net-based
timing-driven placement, Path-based Timing-Driven Placement
- Device Optimization: Device Sizing, Buffer Insertion,
Transistor Ordering
- Topology Optimization: for Wirelength Minimization, for
Pathlength Minimization, for Delay Minimization
- Interconnect Sizing: Local Refinement Based, Dynamic
Programming-Based, Sensitivity Based, Mathematical
Programming, Terminization Optimization
- High-Performance Clock Routing: Zero-Skew, Bounded-Skew,
Buffer and Wire Optimization, Non-Tree routing, Clock
Schedule
Academic Misconduct
Students caught engaging in an academically dishonest practice will
receive a failing grade for the course. University policy on academic
dishonesty will be followed strictly.