Nanoelectronics Research Laboratory |
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Research Groups
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Welcome to the
Purdue University Nanoelectronics
Research Laboratory website! The laboratory is located in the
Department of Electrical &
Computer Engineering at the West Lafayette campus. The primary aim of the laboratory is to develop techniques useful for low power and high performance advanced CMOS IC design. The group also explores aspects of low power processor architecture, noise analysis, noise aware circuit design and VLSI testing. Six different research groups of the laboratory are - Scaled Technologies (Bulk CMOS and SOI), VLSI Signal Processing, Low power and Robust Circuit Design, Low Power Architecture, Nano-electronic Devices and VLSI Testing. The Nanoelectronics Research Laboratory was established around seven years ago in Department of Electrical Engineering, Purdue University. Currently it consists of 26 research staffs including two post-doctoral research assistants. The group is directed by Prof. Kaushik Roy. Major sponsors of the group include Intel, IBM, SRC, NSF, DARPA, Rockwell, Marco GSRC, IBM, HP, ATT/Lucent. The laboratory has produced 21 distinguished alumni to date.
This
homepage contains information about the research activities in the
laboratory and its people. We have posted a list of selected publications
from the laboratory which were contributed to many major journals and
conferences in our field. Should you need to contact the laboratory for any
reason, we will be happy to respond. Please find the contact
information below. Contact information: Nanoelectronics Research Laboratory Room No: MSEE 286, EE237, EE 130, EE 20 1285 EE Building Purdue University West Lafayette, IN 47906 Phone: 1-765-4940759 | 4943372 | 4940750
Fax: 1-765-4943371 For questions, comments etc. please send email to Swarup Bhunia at: bhunias@ecn.purdue.edu Last update: 26 July, 2004. |