Item Analysis - ECE 270 Primary Assessment Exam 3 - Spring 2019 - REVISED

  1. ( 96.3%) Characteristic equation for VF flip-flop...
  2. ( 94.3%) Excitation required for VF flip-flop...
  3. ( 98.3%) Output sequence generated for input sequence given...
  4. ( 93.2%) Embedded binary sequence that is recognized...
  5. ( 95.3%) Duty cycle of clocking signal...
  6. ( 60.1%) Nominal setup time provided...
  7. ( 82.4%) Nominal hold time provided...
  8. ( 99.0%) Nominal clock pulse width...
  9. ( 98.0%) Rise propagation delay of flip-flop...
 10. ( 95.6%) Fall propagation delay of flip-flop...
 11. ( 92.9%) Steady state output for input A=0, B=1...
 12. ( 97.3%) Steady state output for input A=1, B=1...
 13. ( 84.1%) State that cannot occur...
 14. ( 87.5%) Behavior when input A=0, B=0 is continuously applied...
 15. ( 95.6%) Minimum input pulse width required to prevent metastability...
 16. ( 97.6%) Reason a D laatch is called transparent...
 17. ( 52.4%) Statements regarding Mealy and Moore models...
 18. ( 61.8%) Definition of minimum risk...
 19. ( 38.9%) Cause of a random next state...
 20. ( 53.0%) Behavior of SR latch tested in Lab 8...
 21. ( 57.1%) Identification of latch/flip-flop timing behavior...
 22. ( 95.9%) Minimum cost next state equation for Z...
 23. ( 95.3%) Minimum cost next state equation for Y...
 24. ( 90.5%) Minimum cost next state equation for X...
 25. ( 91.2%) Additional states needed for minimum risk synthesis...
 26. ( 59.8%) Mystery machine sensitivity list...
 27. ( 69.6%) Action that occurs on falling edge of clock...
 28. ( 63.2%) Number of distinct states machine cycles through...
 29. (TOSSED) Repeating pattern produced when DIR is 1...
 30. ( 70.9%) Repeating pattern produced when DIR is 0...

 Overall average:  81.63%