Medici References

 

[1] Role of Molecular Surface Passivation in Electrical Transport Properties

Of InAs Nanowires, Q Hang, F Wang, PD Carpenter, D Zemlyanov, D. Janes - Nano Lett, 2008

http://pubs.acs.org/cgi-bin/abstract.cgi/nalefd/2008/8/i01/abs/nl071888t.html

 

[2] An Accurate Analytical SNM Modeling Technique for SRAMs Based on

Butterworth Filter Function, Q Chen, A Guha, K Roy - Proceedings of the 20th International Conference on VLSI., 2007

http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4092110

 

[3] Design Considerations of Silicon Nanowire Biosensors

PR Nair, MA Alam - IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007

http://cobweb.ecn.purdue.edu/~alamgrp/papers-pdf/2007_nair_TED_Design_NanoBiosensor.pdf

 

[4] Incoherent transport through molecules on silicon in the vicinity of a

dangling bond, H Raza, KH Bevan, D Kienle - Physical Review B, 2008

(unable to find freely available pdf)

 

[5] Device-aware yield-centric dual-Vt design under parameter variations in

nanoscale technologies, A Agarwal, K Kang, S Bhunia, JD Gallagher, K Roy - IEEE Transactions on Very Large Scale Integration (VLSI).

http://ieeexplore.ieee.org/iel5/92/4231873/04231874.pdf?tp=&isnumber=&arnumber=4231874

 

[6] Off-State Degradation in Drain-Extended NMOS Transistors: Interface

Damage and Correlation to...D Varghese, H Kufluoglu, V Reddy, H Shichijo, ... MA Alam - ElectronDevices, IEEE Transactions on, 2007

http://cobweb.ecn.purdue.edu/~alamgrp/papers-pdf/2007_varghese_TED_offstate_DENMOS.pdf

 

[7] Reliability-and Process-Variation Aware Design of VLSI Circuits

M Alam, K Kang, BC Paul, K Roy - . Physical and Failure Analysis of Integrated

Circuits, 2007. IPFA 2007 ., 2007

http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4378050

 

[8] Estimation of gate-to-channel tunneling current in ultra-thin oxide

sub-50nm double gate device, S Mukhopadhyay, K Kim, JJ Kim, SH Lo, RV Joshi, CT, K. Roy -Microelectronics Journal, 2007 - Elsevier... Journal Volume 38, Issues 8-9, August-September 2007, Pages 931-941,

(unable to find freely available pdf)

 

[9] Scaling Limits of Double-Gate and Surround-Gate Z-RAM Cells

NZ Butt, MA Alam - Electron Devices, IEEE Transactions on, 2007

http://cobweb.ecn.purdue.edu/%7Ealamgrp/papers-pdf/2007_nauman_TED_SI_ZRAM_Scaling.pdf

 

 

[10] Comparative passivation effects of self-assembled mono-and multilayers

on GaAs junction field effect. K Lee, G Lu, A Facchetti, DB Janes, TJ Marks - Applied Physics Letters,

(unable to find pdf)

 

[11] A 1-kV 4H-SiC Power DMOSFET Optimized for Low on-Resistance

A Saha, JA Cooper - Electron Devices, IEEE Transactions on,

http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?tp=&arnumber=4317746&isnumber=4317723

 

[12] Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body

Bias S Mukhopadhyay, H Mahmoodi, K Roy - Computer-Aided Design of Integrated

Circuits and Systems, ., January 2008

http://ieeexplore.ieee.org/iel5/43/4407552/04358298.pdf?isnumber=4407552&arnumber=4358298

 

[13] Soft Error Trends and New Physical Model for Ionizing Dose Effects in

Double Gate Z-RAM Cell, NZ Butt, PD Yoder, MA Alam - Nuclear Science, IEEE Transactions on, 2007

http://cobweb.ecn.purdue.edu/%7Ealamgrp/papers-pdf/2007_butt_TNS_softerror_ZRAM.pdf

 

Future publications to also cite Medici:

J-Y. Lee, S. Singh, and J. A. Cooper, “Demonstration and Characterization of Bipolar Monolithic Integrated Circuits in 4H-SiC,” to appear in IEEE Transactions on Electron Devices, 2008.

T. Tamaki, G. G. Walden, Y. Sui, and J. A. Cooper, “Numerical Study of the Turn-Off Behavior of High-Voltage 4H-SiC  IGBTs,” to appear in IEEE Transactions on Electron Devices, 2008.

T. Tamaki, G. G. Walden, Y. Sui, and J. A. Cooper, “Optimization of On-State and Switching Performance for 15 – 20 kV 4H-SiC  IGBTs,” to appear in IEEE Transactions on Electron Devices, 2008.

 

 

Taurus references

 

[14] Accurate Modeling and Analysis of Currents in Trapezoidal FinFET Devices

R Rao, A Bansal, J Kim, K Roy, CT Chuang - SOI Conference, 2007 IEEE

International, 2007

http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4357818&arnumber=4357845&count=80&index=26

 

[15] Body Thickness Optimization and Sensitivity Analysis for High

Performance FinFETs. D Lekshmanan, A Bansal, K Roy - Device Research Conference, 2007 65th Annual, 2007.

http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4373617&arnumber=4373664&count=135&index=46

 

[16] High-Performance Device Optimization and Dual-VT Technology Options for

DoubleGate FET. A Bansal, K Kim, JJ Kim, S Mukhopadyay, CT Chuang, K Roy - . Circuit Design and Technology, 2007. ICICDT'07. IEEE ., 2007

http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4299519&arnumber=4299547&count=72&index=27

http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4149023

 

[17] FinFET Based SRAM Design for Low Standby Power Application. T Cakici, K Kim, K Roy - Proceedings of the 8th International Symposium on Quality ., 2007

http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4149023

 

[18] FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve

Stability at iso Area. D Lekshmanan, A Bansal, K Roy - Custom Integrated Circuits Conference, 2007. CICC'07. IEEE, 2007 IEEE 2007 Custom Intergrated Circuits Conference (CICC)

http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4405667&arnumber=4405809&count=200&index=141

 

[19] The effect of process variation on device temperature in finFET circuits

- JH Choi, J Murthy, K Roy - Computer-Aided Design, 2007. ICCAD 2007.

IEEE/ACM ., 2007

http://www.gigascale.org/pubs/1191/p747-choi.pd

 

[20] A generic and reconfigurable test paradigm using Low-cost integrated

Poly-Si TFTs J Li, S Ghosh, K Roy - Test Conference, 2007. ITC 2007. IEEE

International,2007

http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4437546&arnumber=4437622&count=157&index=75

 

[21] A Correlated Diffusion Noise Model for the Field-Effect Transistor

S Lee, KJ Webb - Computer-Aided Design of Integrated Circuits and

Systems,., 2007.

http://ieeexplore.ieee.org/iel5/43/4305238/04305257.pdf?isnumber=4305238&prod=JNL&arnumber=4305257&arSt=1782&ared=1789&arAuthor=Sungjae+Lee%3B+Webb%2C+K.J.

 

[22] Analysis of Options in Double-Gate MOS Technology: A Circuit Perspective

-         RT Cakici, K Roy - Electron Devices, IEEE Transactions on, 2007

-         http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?tp=&arnumber=4383015&isnumber=4383014

 

[23] Modeling and Circuit Synthesis for Independently Controlled Double Gate

FinFET Devices. A Datta, A Goel, RT Cakici, H Mahmoodi, D Lekshmanan, K Roy. -

Computer-Aided Design of Integrated Circuits and Systems, ., 2007

http://ieeexplore.ieee.org/iel5/43/4351994/04352003.pdf?arnumber=4352003

 

[24] Self-Consistent Approach to Leakage Power and Temperature Estimation to

Predict Thermal Runaway in... JH Choi, A Bansal, M Meterelliyoz, J Murthy, K Roy – Computer-Aided Design of Integrated Circuits and Systems, ., 2007

http://ieeexplore.ieee.org/iel5/43/4351994/04351999.pdf?arnumber=4351999

 

[25] Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate

Technologies. A Bansal, JJ Kim, K Kim, S Mukhopadhyay, CT Chuang . K Roy - VLSI

Design, 2008. VLSID 2208. 21st International Conference ., 2008

http://www.ieeexplore.ieee.org/iel5/4450447/4450448/04450491.pdf?isnumber=4450448&prod=CNF&arnumber=4450491&arSt=125&ared=130&arAuthor=Bansal%2C+Aditya%3B+Kim%2C+Jae-Joon%3B+Kim%2C+Keunwoo%3B+Mukhopadhyay%2C+Saibal%3B+Chuang%2C+Ching-Te%3B+Roy%2C+Kaushik

 

 

 

 

[26] Poly-Si Thin-Film Transistors: An Efficient and Low-Cost Option for

Digital Operation. J Li, A Bansal, K Roy - Electron Devices, IEEE Transactions on, 2007

http://ieeexplore.ieee.org/iel5/16/4367582/04367602.pdf?isnumber=4367582&arnumber=4367602

 

[27] Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate

Technologies. A Bansal, JJ Kim, K Kim, S Mukhopadhyay, CT Chuang . K Roy - VLSI

Design, 2008. VLSID 2208. 21st International Conference ., 2008

http://www.ieeexplore.ieee.org/iel5/4450447/4450448/04450491.pdf?isnumber=4450448&prod=CNF&arnumber=4450491&arSt=125&ared=130&arAuthor=Bansal%2C+Aditya%3B+Kim%2C+Jae-Joon%3B+Kim%2C+Keunwoo%3B+Mukhopadhyay%2C+Saibal%3B+Chuang%2C+Ching-Te%3B+Roy%2C+Kaushik

Note (this paper also referenced medici)

 

 

 

Design Compiler References

 

[28] Low-power process-variation tolerant arithmetic units using input-based

elastic clocking D Mohapatra, G Karakonstantis, K Roy - . international symposium on Low power electronics and design, 2007

http://www.gigascale.org/pubs/1082/ErrorResilientExecutionUnits.pdf

 

[29] Tolerance to Small Delay Defects by Adaptive Clock Stretching.

S Ghosh, P NDai, S Bhunia, K Roy - Proceedings of the 13th IEEE

International On-Line Testing ., 2007

http://ieeexplore.ieee.org/iel5/4274802/4274803/04274858.pdf?tp=&isnumber=&arnumber=4274858

 

[30] Low-overhead circuit synthesis for temperature adaptation using dynamic

voltage scheduling. S Ghosh, S Bhunia, K Roy - Proceedings of the conference on Design,automation and test ., 2007

http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4212028

 

[31] Fine-Grained Redundancy in Adders. P Ndai, SL Lu, D Somesekhar, K Roy - . the 8th International Symposium on Quality Electronic Design, 2007

http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4149054

 

[32] CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive

Circuit Synthesis Using... S Ghosh, S Bhunia, K Roy - Computer-Aided Design of Integrated Circuits and Systems, ., 2007

http://ieeexplore.ieee.org/xpls/abs_all.jsp?&arnumber=4352005

 

[33] Design methodology to trade off power, output quality and error

resiliency:application to color. G Karakonstantis, N Banerjee, K Roy, C Chakrabarti - . International Conference on Computer Aided Design,2007.

ICCAD 2007. IEEE/ACM International ., 2007

http://portal.acm.org/citation.cfm?id=1326073.1326114&coll=&dl=

 

 

[see 23] Modeling and Circuit Synthesis for Independently Controlled Double Gate

FinFET Devices - A Datta, A Goel, RT Cakici, H Mahmoodi, D . - Computer-Aided Design of Integrated Circuits and Systems, ., 2007

http://ieeexplore.ieee.org/iel5/43/4351994/04352003.pdf?arnumber=4352003

 

[34] A process variation aware low power synthesis methodology for fixed-point FIR filters. N Banerjee, JH Choi, K Roy - . international symposium on Low power electronics and design, 2007.

http://www.gigascale.org/pubs/1071/LowPowerProcessTolerantFilterDesign.pdf

 

[35] Process variation tolerant low power DCT architecture

N Banerjee, G Karakonstantis, K Roy - Proceedings of the conference on

Design, automation and test ., 2007

http://www.gigascale.org/pubs/995/ProcessTolerantLowPowerDCT.pdf

 

[36] Exploring high-speed low-power hybrid arithmetic units at scaled supply

and adaptive clock- .S Ghosh, K Roy - . of the 2008 conference on Asia and South Pacific design., 2008

http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4483913&arnumber=4484029&count=157&index=115

 

[37] A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive

Clocking S Ghosh, P Ndai, K Roy - Design, Automation and Test in Europe, 2008.

DATE'08, 2008

http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4484624&arnumber=4484707&count=312&index=82

 

[38] Table-lookup based Crossbar Arbitration for Minimal-Routed, 2D Mesh and

Torus Networks. DH Seo, M Thottethodi - . and Distributed Processing Symposium, 2007. IPDPS 2007. ., 2007

http://cobweb.ecn.purdue.edu/~mithuna/pubs/ipdps07.pdf

 

 

 

 

Nanosim references

 

[39] Filter enables real-time performance. A Penner, J Hall, LR Hall, N Jeirath, O Shaikh - Potentials, IEEE, 2007. (work was supervised by M Johnson)

http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4147541&arnumber=4147745

 

(see 28) Low-power process-variation tolerant arithmetic units using input-based

elastic clocking D Mohapatra, G Karakonstantis, K Roy - . international symposium on Low power electronics and design, 2007

http://www.gigascale.org/pubs/1082/ErrorResilientExecutionUnits.pdf

 

(see 36) Exploring high-speed low-power hybrid arithmetic units at scaled supply

and adaptive clock- .S Ghosh, K Roy - Proceedings of the 2008 conference on Asia and South Pacific ., 2008

http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4483913&arnumber=4484029&count=157&index=115

 

 

 

(see 34) A process variation aware low power synthesis methodology for

fixed-point FIR filters. N Banerjee, JH Choi, K Roy - Proceedings of the 2007 international symposium on Low power ., 2007

http://www.gigascale.org/pubs/1071/LowPowerProcessTolerantFilterDesign.pdf

 

 

 

HSPICE References

 

(see 29) Tolerance to Small Delay Defects by Adaptive Clock Stretching

S Ghosh, P NDai, S Bhunia, K Roy - Proceedings of the 13th IEEE

International On-Line Testing ., 2007

http://ieeexplore.ieee.org/iel5/4274802/4274803/04274858.pdf?tp=&isnumber=&arnumber=4274858

 

(see 28) Low-power process-variation tolerant arithmetic units using input-based

elastic clocking D Mohapatra, G Karakonstantis, K Roy - . international symposium on Low power electronics and design, 2007

http://www.gigascale.org/pubs/1082/ErrorResilientExecutionUnits.pdf

 

(see 34) A process variation aware low power synthesis methodology for

fixed-point FIR filters. N Banerjee, JH Choi, K Roy - Proceedings of the 2007 international symposium on Low power ., 2007

http://www.gigascale.org/pubs/1071/LowPowerProcessTolerantFilterDesign.pdf

 

(see 30) Low-overhead circuit synthesis for temperature adaptation using dynamic

voltage scheduling. S Ghosh, S Bhunia, K Roy - Proceedings of the conference on Design, automation and test ., 2007.

http://ieeexplore.ieee.org/iel5/4211748/4211749/04212028.pdf?isnumber=4211749&prod=CNF&arnumber=4212028&arSt=1&ared=6&arAuthor=Ghosh%2C+S.%3B+Bhunia%2C+S.%3B+Roy%2C+K.

 

(see 35) Process variation tolerant low power DCT architecture. N Banerjee, G Karakonstantis, K Roy - Proceedings of the conference on Design, automation and test ., 2007.

http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4211749&arnumber=4211869&count=305&index=119

 

(see 33) Design methodology to trade off power, output quality and error

resiliency: application to color. G Karakonstantis, N Banerjee, K Roy, C Chakrabarti – Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM ., 2007

http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4397223&arnumber=4397266&count=153&index=42

 

(see 20) A generic and reconfigurable test paradigm using Low-cost integrated

Poly-Si TFTs J Li, S Ghosh, K Roy - Test Conference, 2007. ITC 2007. IEEE

International, 2007

http://www.ieeexplore.ieee.org/iel5/4437545/4437546/04437622.pdf?isnumber=4437546&prod=CNF&arnumber=4437622&arSt=1&ared=10&arAuthor=Jing+Li%2C%3B+Ghosh%2C+Swaroop%3B+Roy%2C+Kaushik

 

 

(see 32) CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive

Circuit Synthesis Using... S Ghosh, S Bhunia, K Roy - Computer-Aided Design of Integrated Circuits and Systems, ., 2007

http://ieeexplore.ieee.org/iel5/43/4351994/04352005.pdf

 

(see 22) Analysis of Options in Double-Gate MOS Technology: A Circuit Perspective

RT Cakici, K Roy - Electron Devices, IEEE Transactions on, 2007  

Poly-Si Thin-Film Transistors: An Efficient and Low-Cost Option for Digital

Operation  J Li, A Bansal, K Roy - Electron Devices, IEEE Transactions on, 2007 http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?tp=&arnumber=4383015&isnumber=4383014

 

(see 12) Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body

Bias. S Mukhopadhyay, H Mahmoodi, K Roy - Computer-Aided Design of Integrated

Circuits and Systems, ., 2008

http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4407552&arnumber=4358298

(actually mentions SPICE rather than HSPICE)

 

(see 36) Exploring high-speed low-power hybrid arithmetic units at scaled supply

and adaptive clock... S Ghosh, K Roy - Proceedings of the 2008 conference on Asia and South Pacific ., 2008

http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4483913&arnumber=4484029&count=157&index=115

 

[41] Optimal Dual-Vt Design in Sub-100-nm PD/SOI and Double-Gate Technologies

A Bansal, JJ Kim, K Kim, ... K Roy

(to be published in IEEE Transactions on Electron Devices)

http://ieeexplore.ieee.org/iel5/16/4358746/04476143.pdf?arnumber=4476143