School of Electrical and Computer Engineering

  University Program Member

 

Curriculum use:

ECE337 ASIC Design Laboratory  - Logic synthesis for ASIC design

ECE557 Integrated Circuit/MEMS Fabrication Laboratory  - Device and process modeling

ECE559 MOS VLSI Design  - transistor level circuit simulation of digital IC designs

ECE595B CMOS Analog IC Design - transistor level simulation of analog IC designs

 

Research use:

VLSI and Circuit Design  - Logic synthesis for ASIC design, Device and process modeling, transistor level circuit simulation.

Microelectronics and Nanotechnology  - Device and process modeling

Recent research publications which cite Synopsys tools

 

Grants:

2005 Charles Babbage grant - mixed Solaris/linux compute cluster donated by Sun Microsystems together with the Synopsys, Inc. university program software bundle.

 

This web page is maintained by Mark C. Johnson. Last updated July 2, 2008.

 

 

Synopsys is a registered trademark of Synopsys, Inc.

Information is provided 'as-is' without warranty of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship or otherwise. Please use this information at your own risk.