CadenceTM University Program Member
Currently, the Custom IC bundle, the Custom IC bundle, the Verification Bundle, and the SPB (PCB) bundle are all actively used in the School of Electrical and Computer Engineering at Purdue University. For more information on our use of Cadence tools, the groups and courses using the tools, and for value added items, please see the following links.
Nanoelectronics Research Laboratory – Prof. Kaushik Roy – Custom IC bundle, Digital IC bundle.
Radio Frequency Integrated Circuits – Prof. Saeed Mohammadi – Custom IC bundle.
Adaptive Radio Electronics and Sensors – Prof. Dimitrios Peroulis – Custom IC bundle.
Analog and Mixed Signal Design - Prof. Byunghoo Jung – Custom IC bundle.
VLSI Systems-on-Chip – Prof. Anand Raghunathan – Digital IC bundle, Verification bundle.
Brain-Computer Interface Laboratory - Prof. Pedro Irazoqui - Custom IC bundle
High Energy Physics– Prof. Matthew Jones – Custom IC bundle, SPB (PCB) bundle.
System-on-chip Extension Technologies – Dr. Matthew Swabey, Dr. Mark C. Johnson - Custom IC bundle, Digital IC bundle.
ECE270 Introduction to Digital System Design – SPB (PCB).
ECE362 Microprocessor Systems and Interfacing– SPB (PCB) bundle.
ECE337 ASIC Design Lab – Custom IC bundle, Digital IC bundle.
ECE559 CMOS VLSI Design – Custom IC bundle
ECE455 Integrated Circuit Engineering – Custom IC bundle
ECE456 Digital Integrated Circuit Analysis and Design – Custom IC bundle
ECE595 CMOS Analog IC Design – Custom IC bundle
ECE595 RF MEMS for Intelligent Communications Systems – Custom IC bundle
ECE695 Radio Frequency Integrated Circuits – Custom IC bundle.
ECE695 System-on-Chip Design - Custom IC bundle.
ECE695 Advanced VLSI Design – Custom IC bundle.
EPICS (Engineering Projects in Community Service) - SPB (PCB) bundle
We have also developed a variety of other lab exercises and tutorials, but links are not included because those materials include substantial information about products not produced by Cadence Design Systems, Inc. Contact Mark C. Johnson (email@example.com) for more information. Topics include analog simulation, VHDL simulation, and an ASIC design flow from VHDL to layout and timing verification.
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Mark C. Johnson (firstname.lastname@example.org)