Research Publications

The documents contained in this directory have been made available as a courtesy. Their contents and formats may deviate from those of the published versions. Copyright and all rights therein are maintained by the authors or by other copyright holders. Please respect the copyrights.

Acknowledgments: Much of the research reported here was supported by NSF 9984553-CCR, NSF 0203362-CCR, NSF CCR-0702567, NASA NCC2-1363, SRC 99-TJ-689, SRC Task 947-001, SRC Task 1374.001, SRC Task 1822.001, a grant and equipment donations from Intel Corporation, a Design Automation Conference Scholarship, and Purdue Research Foundation.


Books and Book Chapters

  1. Jason Cong, Lei He, and Cheng-Kok Koh, ``Layout Optimization,'' Chapter 5.1 in Low Power Design in Deep Submicron Electronics, ed. W. Nebel and J. Mermet, NATO ASI Series, Kluwer Academic Publishers, 1997, pp. 205-265.

  2. Cheng-Kok Koh, Evangeline F. Y. Young, and Yao-Wen Chang, ``Global Interconnect Planning,'' Chapter 33 in Handbook of Algorithms for Physical Design Automation, ed. Charles J. Alpert, Dinesh P. Mehta, Sachin S. Sapatnekar, CRC Press, 2009, pp. 645-672.

  3. J.-L. Huang, C.-K. Koh, and S. F. Cauley, ``Logic and Circuit Simulation,'' Chapter 8 in Electronic Design Automation: Synthesis, Verification, and Test, ed. Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng, Elsevier Inc., 2009, pp. 449-512.

  4. C.-K. Koh, J. Jain, and S. F. Cauley, ``Synthesis of Clock and Power/Ground Networks,'' Chapter 13 in Electronic Design Automation: Synthesis, Verification, and Test, ed. Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng, Elsevier Inc., 2009, pp. 751-850.

Journal Articles

  1. Jason Cong and Cheng-Kok Koh, ``Simultaneous Driver and Wire Sizing for Performance and Power Optimization,'' IEEE Trans. on Very Large Scale Integrated (VLSI) Systems (Special Issue on Low-Power Design), 2(4), December 1994, pp. 408-425.

  2. Jason Cong, Lei He, Cheng-Kok Koh, and Patrick H. Madden, ``Performance Optimization of VLSI Interconnect Layout,'' Integration, the VLSI Journal (Invited), 21(1&2), November 1996, pp. 1-94.

  3. Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, and C.-W. Albert Tsao, ``Bounded-Skew Clock and Steiner Routing,'' ACM Trans. on Design Automation of Electronic Systems, Volume 3, Number 3, July 1998, pp. 341-388.

  4. Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, and David B. Janes, ``Stochastic Interconnect Modeling, Power Trends, and Performance Characterization of 3-Dimensional Circuits,'' IEEE Trans. on Electron Devices, 48(4), April 2001, pp. 638-652.

  5. Probir Sarkar and Cheng-Kok Koh, ``Routability-Driven Repeater Block Planning for Interconnect-Centric Floorplanning,'' IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems (Special Issue on Physical Design), 20(5), May 2001, pp. 660-671.

  6. Jason Cong, Lei He, Cheng-Kok Koh, and Zhigang (David) Pan, ``Interconnect Sizing and Spacing with Consideration of Coupling Capacitance,'' IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems , 20(9), September 2001, pp. 1164-1169.

  7. Jason Cong, Cheng-Kok Koh, and Patrick H. Madden, ``Interconnect Layout Optimization under Higher-Order RLC Model for MCM Designs,'' IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, 20(12), December 2001, pp. 1455-1463.

  8. Shiyou Zhao, Kaushik Roy, and Cheng-Kok Koh, ``Decoupling Capacitance Allocation and Its Application to Power Supply Noise Aware Floorplanning'', IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems (Special Issue on Physical Design), 21(1), January 2002, pp. 81-92.

  9. Chung-Wen Albert Tsao and Cheng-Kok Koh, ``UST/DME: A Clock Tree Router for General Skew Constraints,'' ACM Trans. on Design Automation of Electronic Systems, 7(3), July 2002, pp. 359-379.

  10. Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, and David B. Janes, ``Exploring SOI Device Structures and Interconnect Architectures for Low-Power High-Performance Circuits,'' IEE Proceedings, Computers and Digital Techniques, 149(4), July 2002, pp. 137-145.

  11. Guoan Zhong and Cheng-Kok Koh, ``Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects,'' IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, 50(10), October 2003, pp. 1349--1353.

  12. Guoan Zhong, Cheng-Kok Koh, and Kaushik Roy, ``On-chip Interconnect Modeling by Wire Duplication,'' IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, 22(11), November 2003, pp. 1521-1532.

  13. Yiran Chen, Kaushik Roy, and Cheng-Kok Koh, ``Current Demand Balancing: A Technique for Minimization of Current Surge in High Performance Clock-gated Microprocessors,'' IEEE Trans. on Very Large Scale Integrated (VLSI) Systems, 13(1), January 2005, pp. 75-85.

  14. Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, and Kaushik Roy, ``Synthesis of Skewed Logic Circuits,'' ACM Trans. on Design Automation of Electronic Systems, 10(2), April 2005, pp. 205-228.

  15. A. R. Agnihotri, S. Ono, C. Li, M. C. Yildiz, A. Khatkhate, C.-K. Koh, and P. H. Madden, ``Mixed Block Placement via Fractional Cut Recursive Bisection,'' IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, 24(5), May 2005, pp. 748-761.

  16. Ruibing Lu and Cheng-Kok Koh, ``Performance Analysis of Latency Insensitive Systems,'' IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, 25(3), March 2006, pp. 469-483.

  17. Jitesh Jain, Cheng-Kok Koh, and Venkataramanan Balakrishnan, ``Exact and Numerically Stable Closed Form Expressions for Potential Coefficients of Rectangular Conductors,'' IEEE Trans. on Circuits and Systems Part II: Express Briefs, 53(6), June 2006, pp. 458-462. (Corrections appeared in IEEE Trans. on Circuits and Systems Part II: Express Briefs, 54(11), November 2007, pp. 1024-1024. )

  18. Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh, and Tung-Sang Ng, ``Two Algorithms for Fast and Accurate Passivity-Preserving Model Order Reduction,'' IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, 25(10), October 2006, pp. 2062-2075.

  19. Aiqun Cao, Ruibing Lu, Chen Li, and Cheng-Kok Koh, ``Post-Layout Optimization for Synthesis of Domino Circuits,'' ACM Trans. on Design Automation of Electronic Systems, 11(4), October 2006, pp. 797-821.

  20. Ruibing Lu, Aiqun Cao, and Cheng-Kok Koh, ``SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips,'' IEEE Trans. on Very Large Scale Integrated (VLSI) Systems, 15(1), January 2007, pp. 69-79.

  21. Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, and Patrick H. Madden, ``Routability-Driven Placement and White Space Allocation,'' IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, 26(5), May 2007, pp. 858-871.

  22. Stephen Cauley, Jitesh Jain, Cheng-Kok Koh, and Venkataramanan Balakrishnan, ``A scalable distributed method for quantum-scale device simulation,'' Journal of Applied Physics, 101, 123715 (2007) (12 pages).

  23. Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, and Kai-Yuan Chao, ``Fast and optimal redundant via insertion,'' IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, 27(12), December 2008, pp. 2197-2208.

  24. Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, and Hai Li, ``Tolerating process variations in large, set associative caches: The buddy cache,'' ACM Trans. on Architecture and Code Optimization (TACO), 6(2), June 2009, Article 8, 34 pages.

  25. Yiran Chen, Hai Li, Kaushik Roy, and Cheng-Kok Koh, ``Gated Decap: Gate Leakage Control of On-chip Decoupling Capacitors in Scaled Technologies,'' IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 17(12), December 2009, pp. 1749-1752.

  26. Jitesh Jain, Hong Li, Cheng-Kok Koh and Venkataramanan Balakrishnan, ``O(n) Algorithms for Banded Plus Semiseparable Matrices,'' Numerical Methods for Structured Matrices and Applications: Georg Heinig memorial volume, to appear.

  27. Jongwon Lee, Venkataramanan Balakrishnan, Cheng-Kok Koh, and Dan Jiao, ``A Linear-Time Complex-Valued Eigenvalue Solver for Electromagnetic Analysis of Large-Scale On-Chip Interconnect Structures,'' IEEE Trans. on Microwave Theory and Techniques, 57(8), August 2009, pp. 2021-2029.

  28. Yiran Chen, Hai Li, Cheng-Kok Koh, Kaushik Roy, Jing Li, and Guangyu Sun, ``Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance,'' IEEE Trans. on Very Large Scale Integration (VLSI) Systems, to appear.

  29. Jongwon Lee, Venkataramanan Balakrishnan, Cheng-Kok Koh, and Dan Jiao, ``From O(k2N) to O(N): A Fast Complex-Valued Eigenvalue Solver for Large-Scale On-Chip Interconnect Analysis,'' IEEE Trans. on Microwave Theory and Techniques, 57(12), December 2009, pp. 3219-3228.

  30. Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, and Kai-Yuan Chao, ``Optimal Double Via Insertion with On-Track Preference,'' IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, 29(2), February 2010, pp. 318-323.

  31. Yijiang Shen, Ngai Wong, Edmund Y. Lam, and Cheng-Kok Koh, ``Finite Difference Schemes for Heat Conduction Analysis in Integrated Circuit Design and Manufacturing,'' International Journal of Circuit Theory and Applications, to appear.

  32. Stephen Cauley, Venkataramanan Balakrishnan, and Cheng-Kok Koh, ``A Parallel Direct Solver for the Simulation of Large-scale Power/Ground Networks,'' IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, to appear.

Conference/Symposium/Workshop Papers

  1. Jason Cong, Cheng-Kok Koh, and Kwok-Shing Leung, ``Wiresizing with Driver Sizing for Performance and Power Optimization,'' Proc. 1994 International Workshop on Low Power Design, April 1994, pp. 81--86.

  2. Jason Cong and Cheng-Kok Koh, ``Simultaneous Driver and Wire Sizing for Performance and Power Optimization,'' Proc. ACM/IEEE International Conference on CAD-94, November 1994, pp. 206--212.

  3. Jason Cong and Cheng-Kok Koh, ``Minimum-Cost Bounded-Skew Clock Routing,'' Proc. 1995 International Symposium on Circuits and Systems, April 1995, vol. 1, pp. 215--218.

  4. J. Cong, A. B. Kahng, C.-K. Koh, and A. C.-W. Tsao, ``Bounded-Skew Clock and Steiner Routing Under Elmore Delay,'' Proc. ACM/IEEE International Conference on CAD-95, November 1995, pp. 66--71.

  5. J. Cong, C.-K. Koh and K.-S. Leung, ``Simultaneous Buffer and Wire Sizing for Performance and Power Optimization,'' Proc. 1996 International Symposium on Low Power Electronics and Design, August 1996, pp. 271--276.

  6. Jason Cong, Lei He, Kei-Yong Khoo, Cheng-Kok Koh, and Zhigang Pan, ``Interconnect Design for Deep Submicron ICs,'' Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design (Embedded Tutorial), November 1997, pp. 478-485.

  7. Jason Cong, Lei He, Cheng-Kok Koh, and Zhigang Pan, ``Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance,'' Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design, November 1997, pp. 628-633.

  8. Jason Cong and Cheng-Kok Koh, ``Interconnect Layout Optimization Under Higher-Order RLC Model,'' Proc. ACM/IEEE Int'l Conf. on Computer-Aided Design, November 1997, pp. 713-720.

  9. Cheng-Kok Koh and Patrick H. Madden, ``Manhattan or Non-Manhattan? A Study of Alternative VLSI Routing Architectures,'' Proc. Great Lakes Symposium on VLSI, March 2000, pp. 47-52.

  10. Probir Sarkar, Vivek Sundararaman, and Cheng-Kok Koh, ``Routability-Driven Repeater Block Planning for Interconnect-Centric Floorplanning,'' Proc. International Symposium on Physical Design, April 2000, pp. 186-191.

  11. Liqiong Wei, Kaushik Roy, and Cheng-Kok Koh, ``Power Minimization by Simultaneous Dual-Vth Assignment and Gate-Sizing,'' Proc. IEEE 2000 Custom Integrated Circuits Conference, May 2000, pp. 413-416.

  12. Alexandre Solomatnikov, Dinesh Somasekhar, Kaushik Roy, and Cheng-Kok Koh, ``Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family,'' Proc. International Conference on Computer Design, September 2000, pp. 241-246.

  13. Shiyou Zhao, Kaushik Roy, and Cheng-Kok Koh, ``Estimation of Inductive and Resistive Switching Noise on Power Supply Network in Deep Sub-micron CMOS Circuits,'' Proc. International Conference on Computer Design, September 2000, pp. 65-72.

  14. Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, and David B. Janes, ``Stochastic Wire-Length Distribution and Delay Distribution of 3-Dimensional Circuits,'' Proc. International Conference on Computer-Aided Design, November 2000, pp. 208-213.

  15. Chung-Wen Albert Tsao and Cheng-Kok Koh, ``UST/DME: A Clock Tree Router for General Skew Constraints,'' Proc. International Conference on Computer-Aided Design, November 2000, pp. 400-405.

  16. Guoan Zhong, Cheng-Kok Koh, and Kaushik Roy, ``A Twisted-Bundle Layout Structure for Minimizing Inductive Coupling Noise,'' Proc. International Conference on Computer-Aided Design, November 2000, pp. 406-411.

  17. Shiyou Zhao, Kaushik Roy, and Cheng-Kok Koh, ``Frequency Domain Analysis of Switching Noise on Power Supply Network,'' Proc. International Conference on Computer-Aided Design, November 2000, pp. 487-492.

  18. Probir Sarkar and Cheng-Kok Koh, ``Repeater Block Planning under Simultaneous Delay and Transition Time Constraints,'' Proc. 2001 Design, Automation and Test in Europe, March 2001, pp. 540-544.

  19. Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, and David B. Janes, ``Power Trends and Performance Characterization of 3-Dimensional Integration for Future Technology Generations,'' Proc. 2001 International Symposium on Quality Electronic Design, March 2001, pp. 217-222.

  20. Shiyou Zhao, Kaushik Roy, and Cheng-Kok Koh, ``Decoupling Capacitance Allocation for Power Supply Noise Suppression,'' Proc. 2001 International Symposium on Physical Design, April 2001, pp. 66-71.

  21. Rui Wang, Kaushik Roy, and Cheng-Kok Koh, ``Short-Circuit Power Analysis of an Inverter Driving an RLC Load,'' Proc. 2001 International Symposium on Circuits and Systems, May 2001, Volume 4, pp. 886-889.

  22. Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, and David B. Janes, ``Power Trends and Performance Characterization of 3-Dimensional Integration,'' Proc. 2001 International Symposium on Circuits and Systems, May 2001, Volume 4, pp. 414-417.

  23. Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, and David B. Janes, ``Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration,'' Proc. 2001 Design Automation Conference, June 2001, pp. 846-851.

  24. Venkataramanan Balakrishnan, Qing Su, and Cheng-Kok Koh, ``Efficient Balance-and-Truncate Model Reduction for Large-Scale System,'' Proc. 2001 American Control Conference, June 2001, Volume 6, pp. 4746-4751.

  25. Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, and Kaushik Roy, ``Selectively Clocked Skewed Logic (SCSL): A Robust Low-Power Logic Style for High-Performance Applications,'' Proc. International Symposium on Low Power Electronics and Design, August 2001, pp. 267-270.

  26. Woopyo Jeong, Kaushik Roy, and Cheng-Kok Koh, ``High-Performance Low-Power Carry Select Adder using Dual Transition Skewed Logic,'' Proc. 27th European Solid-State Circuits Conference (ESSCIRC), September 2001, pp. 145-148.

  27. Qing Su, Venkataramanan Balakrishnan, and Cheng-Kok Koh, ``Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods,'' Proc. 15th International Conference on VLSI Design and 7th Asia and South Pacific Design Automation Conference, January 2002, pp. 311-316.

  28. Shiyou Zhao, Kaushik Roy, and Cheng-Kok Koh, ``Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement,'' Proc. 15th International Conference on VLSI Design and 7th Asia and South Pacific Design Automation Conference, January 2002, pp. 489-495.

  29. Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, and Kai-Yuan Chao, ``Flip-Flop and Repeater Insertion for Early Interconnect Planning,'' Proc. Design, Automation and Test in Europe Conference, March 2002, pp. 690-695.

  30. Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok Koh, and Kaushik Roy, ``Model Reduction in Time-Domain using Laguerre Polynomials and Krylov Methods,'' Proc. Design, Automation and Test in Europe Conference, March 2002, pp. 931-935.

  31. Aiqun Cao, Naran Srisantana, Cheng-Kok Koh, and Kaushik Roy, ``Synthesis of Selectively Clocked Skewed Logic Circuits,'' Proc. International Symposium on Quality Electronic Design, March 2002, pp. 229-234.

  32. Wai-Ching Douglas Lam, and Cheng-Kok Koh, and Chung-Wen Albert Tsao, ``Power Supply Noise Suppression via Clock Skew Scheduling,'' Proc. International Symposium on Quality Electronic Design, March 2002, pp. 355-360.

  33. Qing Su, Venkataramanan Balakrishnan, and Cheng-Kok Koh, ``A Factorization-Based Framework for Passivity-Preserving Model Reduction of RLC Systems,'' Proceedings of Design Automation Conference, June 2002, pp. 40-45.

  34. Guoan Zhong and Cheng-Kok Koh, ``Exact Closed Form Formula for Partial Mutual Inductances of On-Chip Interconnects,'' Proceedings of International Conference on Computer Design, September 2002, pp. 428-433.

  35. Guoan Zhong, Cheng-Kok Koh, and Kaushik Roy, ``Fast On-Chip Interconnect Modeling by Wire Duplication,'' Proceedings of International Conference on Computer-Aided Design, San Jose, CA, November 2002, pp. 341-346.

  36. Guoan Zhong, Cheng-Kok Koh, and Kaushik Roy, ``A Metric for Analyzing Effective On-Chip Inductive Coupling,'' Proceedings of Asia and South Pacific Design Automation Conference, Kitakyushu, Japan, January 2003, pp. 156-161.

  37. Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, and Kaushik Roy, ``Integer Linear Programming-Based Synthesis of Skewed Logic Circuits,'' Proceedings of Asia and South Pacific Design Automation Conference, Kitakyushu, Japan, January 2003, pp. 820-823.

  38. Ruibing Lu and Cheng-Kok Koh, ``Interconnect Planning with Local Area Constrained Retiming,'' Proceedings of Design, Automation and Test in Europe Conference, Munich, Germany, March 2003, pp. 442-447.

  39. Wai-Ching Douglas Lam, Cheng-Kok Koh, and Chung-Wen Albert Tsao, ``Clock Scheduling for Power Supply Noise Suppression Using Genetic Algorithm with Selective Gene Therapy,'' Proceedings of 2003 International Symposium on Quality Electronic Design, San Jose, CA, March 2003, pp. 327-332.

  40. Aiqun Cao and Cheng-Kok Koh, ``Non-Crossing Ordered BDD for Physical Synthesis of Regular Circuit Structure,'' International Workshop on Logic and Synthesis, Laguna Beach, CA, May 2003, pp. 200-206.

  41. Guoan Zhong, Cheng-Kok Koh, Venkataramanan Balakrishnan, and Kaushik Roy, ``An Adaptive Window-Based Susceptance Extraction and its Efficient Implementation,'' Proceedings of Design Automation Conference, Anaheim, CA, June 2003, pp. 728-731.

  42. Yiran Chen, Kaushik Roy, and Cheng-Kok Koh, ``Switching Balancing Approach for Power-Supply Noise Reduction in High Performance Microprocessor,'' Proc. International Symposium on Low Power Electronics and Design, August 2003, pp. 229-234.

  43. Aiqun Cao and Cheng-Kok Koh, ``Non-Crossing OBDDs for Mapping to Regular Circuit Structures,'' Proc. International Conference on Computer Design, October 2003, pp. 338-343.

  44. Ruibing Lu and Cheng-Kok Koh, ``SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips,'' Proc. International Conference on Computer Aided Design, November 2003, pp. 8-12.

  45. Ruibing Lu and Cheng-Kok Koh, ``Performance Optimization of Latency Insensitive Systems through Buffer Queue Sizing,'' Proc. International Conference on Computer Aided Design, November 2003, pp. 227-231.

  46. Ruibing Lu and Cheng-Kok Koh, ``A High Performance Bus Communication Architecture through Bus Splitting,'' Proceedings of Asia and South Pacific Design Automation Conference, Yokohama, Japan, January 2004, pp. 751-755.

  47. Yiran Chen, Kaushik Roy, and Cheng-Kok Koh, ``Priority Assignment Optimization for Minimization of Current Surge in High Performance Power Efficient Clock-gated Microprocessor,'' Proceedings of Asia and South Pacific Design Automation Conference, Yokohama, Japan, January 2004, pp. 894-899.

  48. Ateen Khatkhate, Chen Li, Ameya R. Agnihotri, Mehmet C. Yildiz, Satoshi Ono, Cheng-Kok Koh, and Patrick H. Madden, ``Recursive Bisection Based Mixed Block Placement,'' International Symposium on Physical Design, Phoenix, Arizona, April 2004, pp. 84-89.

  49. Ngai Wong, Venkataramanan Balakrishnan, Cheng-Kok Koh, and Tung-Sang Ng, ``A Fast Newton/Smith Algorithm for Solving Algebraic Riccati Equations and its Application in Model Order Reduction,'' International Conference on Acoustics, Speech, and Signal Processing, Montreal, Canada, May 2004, pp. 53-56.

  50. Aiqun Cao and Cheng-Kok Koh, ``Decomposition of BDDs with Application to Physical Mapping of Regular PTL Circuits,'' International Workshop on Logic and Synthesis, Temecula, CA, June 2004, pp. 244-249.

  51. Ngai Wong, Venkataramanan Balakrishnan, and Cheng-Kok Koh, ``Passivity-Preserving Model Reduction via a Computationally Efficient Project-and-Balance Scheme,'' Design Automation Conference, San Diego, CA, June 2004, pp. 369-374.

  52. Aiqun Cao and Cheng-Kok Koh, ``Post-Layout Logic Optimization of Domino Circuits,'' Design Automation Conference, San Diego, CA, June 2004, pp. 820-825.

  53. Jitesh Jain, Cheng-Kok Koh, and Venkataramanan Balakrishnan, ``Fast Simulation of VLSI Interconnects,'' International Conference on Computer Aided Design, San Jose, CA, November 2004, pp. 93-98.

  54. Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, and Patrick H. Madden, ``Routability-Driven Placement and White Space Allocation,'' International Conference on Computer Aided Design, San Jose, CA, November 2004, pp. 394-401.

  55. Aiqun Cao, Ruibing Lu, and Cheng-Kok Koh, ``Post-Layout Logic Duplication for Synthesis of Domino Circuits with Complex Gates,'' Proceedings of Asia and South Pacific Design Automation Conference, Shanghai, People's Republic of China, January 2005, pp. 260-265.

  56. Chen Li, Cheng-Kok Koh, and Patrick H. Madden, ``Floorplan Management: Incremental Placement for Gate Sizing and Buffer Insertion,'' Proceedings of Asia and South Pacific Design Automation Conference, Shanghai, People's Republic of China, January 2005, pp. 349-354.

  57. Hong Li, Venkataramanan Balakrishnan, Cheng-Kok Koh, and Guoan Zhong, ``Compact and Stable Modeling of Partial Inductance and Reluctance Matrices,'' Proceedings of Asia and South Pacific Design Automation Conference, Shanghai, People's Republic of China, January 2005, pp. 507-510.

  58. Wai-Ching Douglas Lam and Cheng-Kok Koh, ``Process Variation Robust Clock Tree Routing,'' Proceedings of Asia and South Pacific Design Automation Conference, Shanghai, People's Republic of China, January 2005, pp. 606-611.

  59. Ruibing Lu, Aiqun Cao, and Cheng-Kok Koh, ``Improving the Scalability of SAMBA Bus Architecture,'' Proceedings of Asia and South Pacific Design Automation Conference, Shanghai, People's Republic of China, January 2005, pp. 1164-1167.

  60. J. R. Minz, S. K. Lim, and C.-K. Koh, ``3D Module Placement for Congestion and Power Noise Reduction,'' Great Lakes Symposium on VLSI, April 2005, pp. 458-461.

  61. Yiran Chen, Hai Li, Kaushik Roy, and Cheng-Kok Koh, ``Cascaded Carry-Select Adder (C2SA): A New Structure for Low-Power CSA Design,'' International Symposium on Low Power Electronics Design, August 2005, pp. 115-118.

  62. Yiran Chen, Hai Li, Cheng-Kok Koh and Kaushik Roy, ``Gated Decap: A Technique to Reduce Gate Leakage in Decoupling Capacitors in Scaled Technologies'', 2005 IEEE Custom Integrated Circuits Conference, September 2005, pp. 775-778.

  63. Winson Yongxin Zhu, Weng-Fai Wong, and Cheng-Kok Koh, ``A Performance and Power Co-optimization Approach for Modern Processors,'' 5th International Conference on Computer and Information Technology (CIT2005), Shanghai, China, September 2005, pp. 822-828.

  64. Wai-Ching Douglas Lam, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan, and Yiran Chen, ``Statistical Based Link Insertion for Robust Clock Network Design,'' International Conference on Computer Aided Design, San Jose, CA, November 2005, pp. 587-590.

  65. Hai Li, Yiran Chen, Kaushik Roy and Cheng-Kok Koh, ``SAVS: A Self-Adaptive Variable Supply-Voltage Technique for Process-Tolerant and Power-Efficient Multi-issue Superscalar Processor Design,'' Proceedings of Asia and South Pacific Design Automation Conference, January 2006, pp. 158-163.

  66. Jitesh Jain, Stephen F. Cauley, Cheng-Kok Koh, and Venkataramanan Balakrishnan, ``SASIMI: Sparsity Aware Simulation of Interconnect-Dominated Circuits with Non-Linear Devices,'' Proceedings of Asia and South Pacific Design Automation Conference, January 2006, pp. 422-427.

  67. Ya-Chi Yang, Cheng-Kok Koh, and Venkataramanan Balakrishnan, ``Adaptive Admittance-based Conductor Meshing for Interconnect Analysis,'' Proceedings of Asia and South Pacific Design Automation Conference, January 2006, pp. 509-514.

  68. Ruilin Wang, Cheng-Kok Koh, Byunghoo Jung, and William J. Chappell, ``Clock Generation and Distribution Using Traveling-Wave Oscillators with Reflection and Regeneration,'' Proceedings of IEEE Custom Integrated Circuit Conference, San Jose, CA, September 2006, pp. 781-784.

  69. Hong Li, Venkataramanan Balakrishnan, and Cheng-Kok Koh, ``Stable and Compact Inductance Modeling of 3-D Interconnect Structures,'' Proceedings of International Conference on Computer Aided Design, San Jose, CA, November 2006, pp. 1-6.

  70. Hong Li, Cheng-Kok Koh, Venkataramanan Balakrishnan, and Yiran Chen, ``Statistical Timing Analysis Considering Spatial Correlations,'' Proc. International Symposium on Quality Electronic Design, San Jose, CA, March 26-28 2007, pp. 102-107.

  71. Hong Li, Jitesh Jain, Venkataramanan Balakrishnan, and Cheng-Kok Koh, ``Efficient Analysis of Large-Scale Power Grids based on a Compact Cholesky Factorization,'' Proc. International Symposium on Quality Electronic Design, San Jose, CA, March 26-28 2007, pp. 627-632.

  72. Chen Li and Cheng-Kok Koh, ``Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement,'' Proc. International Symposium on Quality Electronic Design, San Jose, CA, March 26-28 2007, pp 829-834. Also in Proceedings of Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), Nagoya, Japan, Apr 3-4, 2006, pp. 423-428.

  73. Yiran Chen, Hai Li, Jing Li, and Cheng-Kok Koh, ``Variable-latency Adder (VL-Adder): New Arithmetic Circuit Design Practice to Overcome NBTI,'' Proceedings of International Symposium on Low Power Electronics and Design, Portland, OR, August 27-29 2007, pp. 195-200.

  74. Weng-Fai Wong, Yiran Chen, Hai Li, and Cheng-Kok Koh, ``VOSCH: Voltage Scaled Cache Hierarchies,'' Proc. International Conference on Computer Design, Lake Tahoe, CA, October 2007, pp. 496-503.

  75. Ruilin Wang and Cheng-Kok Koh, ``A Frequency-domain Technique for Statistical Timing Analysis of Clock Meshes,'' Proceedings of International Conference on Computer Aided Design, San Jose, CA, November 2007, pp. 334-339.

  76. Hong Li, Jitesh Jain, Cheng-Kok Koh, and Venkataramanan Balakrishnan, ``A Fast Band-matching Technique for Interconnect Inductance Modeling,'' Proceedings of International Conference on Computer Aided Design, San Jose, CA, November 2007, pp. 568-571.

  77. Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang and Kai-Yuan Chao, ``Optimal Post-Routing Redundant Via Insertion,'' Proceedings of International Symposium on Physical Design, Portland, OR, April 2008, pp. 111-117.

  78. Jitesh Jain, Hong Li, Cheng-Kok Koh, and Venkataramanan Balakrishnan, ``A Fast Band Matching Technique for Impedance Extraction,'' Proceedings of International Symposium on Circuits and Systems, Seattle, WA, May 2008, pp. 2981-2984.

  79. Jongwon Lee, Venkataramanan Balakrishnan, Cheng-Kok Koh, and Dan Jiao, ``A Linear-Time Eigenvalue Solver for Finite-Element-Based Analysis of Large-Scale Wave Propagation Problems in On-Chip Interconnect Structures,'' IEEE International Symposium on Antennas and Propagation, July 2008, pp. 1-4.

  80. Kalliopi Tsota, Cheng-Kok Koh, and Venkataramanan Balakrishnan, ``Guiding Global Placement with Wire Density,'' Proceedings of International Conference on Computer Aided Design, San Jose, CA, November 2008, pp. 212-217.

  81. Jongwon Lee, Venkataramanan Balakrishnan, Cheng-Kok Koh, and Dan Jiao, ``A Linear-Time Complex-Valued Eigenvalue Solver for Large-Scale Full-Wave Extraction of On-Chip Interconnect Structures," 2009 International Annual Review of Progress in Applied Computational Electromagnetics (ACES), March, 2009, 5 pages.

  82. Jongwon Lee, Venkataramanan Balakrishnan, Cheng-Kok Koh, and Dan Jiao, ``From O(k2N) to O(N): A Fast Complex-Valued Eigenvalue Solver for Large-Scale On-Chip Interconnect Analysis,'' Proceedings of International Microwave Symposium, Boston, MA, June 2009, 4 pages.

  83. Wenwen Chai, Dan Jiao, and Cheng-Kok Koh, ``A Direct Integral-Equation Solver of Linear Complexity for Large-Scale 3D Capacitance and Impedance Extraction,'' Proceedings of Design Automation Conference, San Francisco, CA, July 2009, to appear.

  84. Cheng-Kok Koh, Weng-Fai Wong, Yiran Chen, and Hai Li, ``The Salvage Cache: A Fault-Tolerant Cache Architecture for Next-generation Memory Technologies,'' Proceedings of International Conference on Computer Design, Lake Tahoe, CA, October 2009, to appear.

  85. Kalliopi Tsota, Cheng-Kok Koh, and Venkataramanan Balakrishnan, ``A Study of Routability Estimation and Clustering in Placement,'' Proceedings of International Conference on Computer-Aided Design, San Jose, CA, November 2009, to appear.

Thesis

  1. Cheng-Kok Koh, ``Steiner Problem in the Octilinear Routing Model,'' Master Thesis, National University of Singapore, submitted in August 1995, revised and accepted in May 1996.

  2. Cheng-Kok Koh, ``VLSI Interconnect Layout Optimization,'' PhD Thesis, University of California, Los Angeles, August 1998.