BOOK

A. Raghunathan, N. K. Jha, and S. Dey, "High-level power analysis and optimization", Kluwer Academic Publishers, 1997.

BOOK CHAPTERS

  1. A. Raghunathan, S. Dey, and N. K. Jha, "Glitch analysis and reduction in register-transfer level power optimization", in Low Power CMOS Design (A. Chandrakasan and R. Brodersen - Editors), IEEE Press, 1997.

  2. D. Panigrahi, S. Dey, and A. Raghunathan, "Network-aware content shaping for energy efficient wireless web access", in System-level power optimization for wireless multimedia communication (R. Karri and D. J. Goodman - Editors), Kluwer Academic Publishers, 2002.

  3. P. Ashar, S. T. Chakradhar, A. Gupta, J. Henkel, A. Raghunathan, and K. Wakabayashi, "NEC and ICCAD - EDA partners in success", in The Best of ICCAD (A. Kuehlmann - Editor), Kluwer Academic Publishers, 2002.

  4. S. Ravi, A. Raghunathan, S. Hattangady, and J.-J Quisquater, "Emerging Challenges in Designing Secure Mobile Appliances" in Ambient Intelligence: Impact on Embedded System Design (T. Basten, M. Geilen, and H. de Groot - Editors), Kluwer Academic Publishers, November 2003.

  5. T. K. Tan, A. Raghunathan, and N. J. Jha, "Software architectural transformations: A new approach to low energy embedded software", in Embedded Software for SoC (A. A. Jerraya, S. Yoo, and N. Wehn - Editors), Kluwer Academic Publishers, 2003.

  6. K. Lahiri, S. Dey, and A. Raghunathan, "Design of Communication Architectures for High-performance and Energy-efficient System-on-chips," in Multiprocessor Systems-on-chips (W. Wolf and A. A. Jerraya - Editors), Morgan Kaufman Publishers, September 2004.

  7. D. Arora, Srivaths Ravi, Anand Raghunathan, and Niraj K. Jha, "Architectural Enhancements for Secure Embedded Processing," in Security and Embedded Systems (D. Serpanos and R. Giladi - Editors), IOS Press, February 2006.

  8. F. Sun, S. Ravi, A. Raghunathan, and Niraj K. Jha, ``A framework for extensible processor based {MPSoC} design,'' in Embedded Processors: A Low Power Perspective} (J. Henkel and S. Parameswaran - Editors), Springer, April 2007.


CONFERENCE TUTORIALS

  1. K. Roy, R. Roy, and A. Raghunathan, "Low-Power IC Design", Full-day tutorial, Asia and South Pacific Design Automation Conference (ASP-DAC), February 1998.

  2. K. Roy, A. Raghunathan, and S. Dey, "Low Power Design Methodologies for System-on-Chips", Full-day tutorial, IEEE International Conference on VLSI Design, January 1999.

  3. A. Raghunathan, S. Dey, D. Gonzales, T. Mudge, K. Roy, "Low Power System Design: Applications, Architectures, and Design Methodologies," full-day tutorial, ACM/IEEE Design Automation Conference, June 2000.

  4. A. Raghunathan, S. Dey, and S. Sarkar, "Low-power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies," full-day tutorial, IEEE International Conf. on VLSI Design, January 2001.

  5. S. Dey, A. Raghunathan, ``Low-power Mobile Wireless Communication System Design," half-day tutorial, Design Automation and Test in Europe (DATE) , March 2001.

  6. A. Raghunathan, S. Ravi, D. Arora, and S. Mangard, ``Designing Secure SoCs'', full-day tutorial, International Conference on VLSI Design , January 2007.

  7. A. Raghunathan, S. Ravi, E. Peeters, and S. Bhunia, ``Designing Secure SoCs'', full-day tutorial, International Conference on VLSI Design , January 2013.


INVITED PRESENTATIONS

  1. S. Dey, A. Raghunathan, and R. Roy, "Considering testability during high-level design", Invited Embedded tutorial, Asia and South Pacific Design Automation Conference (ASP-DAC), February 1998.

  2. K. Lahiri, A. Raghunathan, S. Dey, and D. Panigrahi, "Battery-driven system design: A new frontier in low power design", Invited Embedded tutorial, Asia and South Pacific Design Automation Conference (ASP-DAC) / International Conference on VLSI Design , January 2002.

  3. S. Ravi, A. Raghunathan, and N. Potlapally, "Securing wireless data: System Architecture Challenges,", Invited Special Session Presentation, IEEE International Symposium on System Synthesis (ISSS) , October 2002.

  4. S. Ravi, A. Raghunathan, and S. T. Chakradhar, "Embedding Security in Wireless Embedded Systems", Invited Embedded tutorial, International Conference on VLSI Design , January 2003.

  5. S. Ravi and A. Raghunathan, "Securing your mobile appliance: New challenges for the embedded system designer", Hot Topic Presentation, Design, Automation, and Test in Europe (DATE), March 2003.

  6. S. Ravi, A. Raghunathan, and S. T. Chakradhar, "Tamper-resistant embedded system design", Invited Embedded tutorial, International Conference on VLSI Design , January 2004.

  7. A. Raghunathan, "Secure Embedded System Design: A Tale of Three Gaps", Invited Presentation, International Workshop on Logic and Synthesis , June 2005.

  8. D. Arora, Srivaths Ravi, Anand Raghunathan, and Niraj K. Jha, "Architectural Enhancements for Secure Embedded Processing," NATO Workshop on Security in Embedded Systems, August 2005.

  9. A. Raghunathan, "Security for Mobile Wireless Applications", invited talk, Workshop on Secure Embedded Implementations, Design, Automation, and Test Europe (DATE), April 2007.
  10. N. Banerjee, S. Chandra, S. Ghosh, S. Dey, A. Raghunathan, and K. Roy, "Coping with Variations through System-Level Design", Invited Embedded tutorial, International Conference on VLSI Design , January 2009.

  11. G. Martin, A. Raghunathan, and S. Parameswaran, "Embedded Processors, Methods and Applications", Invited Embedded Tutorial, International Conference on Computer-Aided Design (ICCAD), November 2009.

  12. A. Raghunathan and K. Roy, "Approximate Computing: Embracing Unreliability for Efficient Computing", Invited Presentation, Dagstuhl Symposium on Verifying Reliability, August 2012.

  13. M. Mozaffari Kermani, M. Zhang, A. Raghunathan, and N. K Jha, "Emerging Frontiers in Embedded Security", Invited Embedded tutorial, International Conference on VLSI Design , January 2013.

  14. A. Raghunathan, "Securing the Internet of Things - A Grand Challenge in Information Security", Distinghuished Invited Speaker, International Symposium on Cyber Security, January 2013.

  15. A. Raghunathan, "Approximate Computing - Computing Efficiently with Good Enough Results", Invited Presentation, International Online Testing Symposium, July 2013.

  16. A. Raghunathan, "Approximate Computing at Purdue", Invited Presentation, Intel Workshop on Approximate Computing, August 2013.

  17. A. Raghunathan, "Programmable Architecture for Recognition, Mining, and Synthesis", Invited Presentation, Qualcomm October 2013.


JOURNALS

  1. A. Raghunathan, P. Ashar and S. Malik, "Test generation for cyclic combinational circuits", IEEE Transactions on Computer-Aided Design, November 1995.

  2. I. Ghosh, A. Raghunathan, and N. K. Jha, "Design-for-hierarchical-testability of register-transfer level circuits obtained by behavioral synthesis", IEEE Transactions on Computer-Aided Design, September 1997.

  3. S. T. Chakradhar and A. Raghunathan, "Bottleneck elimination algorithm for dynamic compaction and test cycles reduction", IEEE Transactions on Computer-Aided Design, October 1997.

  4. A. Raghunathan and N. K. Jha, "SCALP: An iterative improvement based low power datapath synthesis system", IEEE Transactions on Computer-Aided Design, November 1997.

  5. I. Ghosh, A. Raghunathan, and N. K. Jha, "A design-for-testability technique for register-transfer level circuits using control/data flow extraction", IEEE Transactions on Computer-Aided Design, August 1998.

  6. S. Dey, A. Raghunathan and K. Wagner, "Design for testability techniques at the behavioral and register-transfer levels", Journal of Electronic Testing: Theory and Applications (JETTA) , October 1998.

  7. G. Lakshminarayana, A. Raghunathan, N. K. Jha, and S. Dey, "Power management in high-level synthesis", IEEE Transactions on VLSI Systems, Special Issue on Low-Power Electronics and Design, March 1999.

  8. I. Ghosh, A. Raghunathan, and N. K. Jha, "Hierarchical test generation and design for hierarchical testability of ASPPs and ASIPs", IEEE Transactions on Computer-Aided Design, March 1999.

  9. A. Raghunathan, S. Dey, and N. K. Jha, "Register-transfer level power optimization techniques with emphasis on glitch analysis and reduction", IEEE Transactions on Computer-Aided Design, August 1999.

  10. S. Dey, A. Raghunathan, N. K. Jha, and K. Wakabayashi, "Controller-based power management for control-flow intensive designs", IEEE Transactions on Computer-Aided Design, October 1999.

  11. G. Lakshminarayana, A. Raghunathan, and N. K. Jha, "Incorporating speculative execution into scheduling of control-flow intensive designs", IEEE Transactions on Computer-Aided Design, March 2000.

  12. G. Lakshminarayana, A. Raghunathan, and N. K. Jha, "Behavioral synthesis of fault-secure data paths based on aliasing probability analysis", IEEE Transactions on Computers, September 2000.

  13. K. Lahiri, A. Raghunathan, and S. Dey, ``System-level performance analysis for designing on-chip communication architectures," IEEE Transactions on Computer-Aided Design, June 2001.

  14. M. Lajolo, A. Raghunathan, S. Dey, and L. Lavagno, "Co-simulation based power estimation for system-on-chip design," IEEE Transactions on VLSI Systems, June 2002.

  15. K. Lahiri, A. Raghunathan, and S. Dey, ``Communication-based power management," IEEE Design & Test of Computers (Special issue - "Best of practice" papers from the 2002 Design Automation Conference), May-June 2002.

  16. T. K. Tan, A. Raghunathan, G. Lakshminarayana, and N. K. Jha, "High-level energy macro-modeling of embedded software", IEEE Transactions on Computer-Aided Design, September 2002.

  17. R. P. Dick, G. Lakshminarayana, A. Raghunathan, and N. K. Jha, ``Analysis of power dissipation in embedded systems using real-time operating systems," IEEE Transactions on Computer-Aided Design, May 2003.

  18. A. Raghunathan, S. Dey, and N. K. Jha, "High-level macro-modeling and estimation techniques for switching activity and power consumption", IEEE Transactions on VLSI Systems, August 2003.

  19. T. K. Tan, A. Raghunathan, and N. K. Jha, "A simulation framework for energy consumption analysis of OS-driven embedded applications", IEEE Transactions on Computer-Aided Design, September 2003.

  20. G. Lakshminarayana, A. Raghunathan, K. S. Khouri, N. K. Jha, and S. Dey, "Common Case Computation: A new paradigm for energy and performance optimization", IEEE Transactions on Computer-Aided Design, January 2004.

  21. F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, ``Custom instruction synthesis for extensible processor platforms," IEEE Transactions on Computer-Aided Design, February 2004.

  22. Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, "A hybrid energy estimation technique for extensible processors", IEEE Transactions on Computer-Aided Design, May 2004.

  23. K. Lahiri, A. Raghunathan, G. Lakshminarayana, and S. Dey, ``Design of high-performance System-on-chips using Communication Architecture Tuners," IEEE Transactions on Computer-Aided Design, May 2004.

  24. K. Lahiri, A. Raghunathan, and S. Dey, ``Design Space Exploration for Optimizing On-Chip Communication Networks," IEEE Transactions on Computer-Aided Design, June 2004.

  25. K. Lahiri, A. Raghunathan, and S. Dey, ``System-Level Power Profiling for Battery-Driven Embedded System Design," IEEE Transactions on Computer-Aided Design, June 2004.

  26. W. Wang, A. Raghunathan, G. Lakshminarayana, and N. K. Jha, "Energy-efficient Hardware Through Input Space Adaptive Design," IEEE Transactions on VLSI Systems, June 2004.

  27. W. Wang, A. Raghunathan, N. K. Jha, and S. Dey, "Resource budgeting for multiprocess high level synthesis," IEEE Transactions on Computer-Aided Design, July 2004.

  28. S. Ravi, A. Raghunathan, P. Kocher, and S. Hattangady, ``Challenges in Designing Secure Embedded Systems," Invited paper, ACM Transactions on Embedded Computing Systems (Special Issue on Security), August 2004.

  29. T. K. Tan, A. Raghunathan, and N. K. Jha, "Energy macro-modeling of embedded operating systems", ACM Transactions on Embedded Computing Systems, February 2005.

  30. C. Huang, S. Ravi, A. Raghunathan, and N. K. Jha, "Generation of distributed logic-memory architectures through high-level synthesis", IEEE Transactions on Computer-Aided Design, November 2005.

  31. W. Wang, A. Raghunathan, G. Lakshminarayana, and N. K. Jha, "Input space adaptive optimization for embedded software synthesis," IEEE Transactions on Computer-Aided Design, November 2005.

  32. N. Potlapally, S. Ravi, A. Raghunathan, and N. K. Jha, "A study of the energy consumption characteristics of cryptographic algorithms and security protocols", ACM Transactions on Mobile Computing, March-April 2006.

  33. F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, ``Application-specific heterogeneous multiprocessor synthesis using extensible processors," IEEE Transactions on Computer-Aided Design, September 2006.

  34. C. Huang, S. Ravi, A. Raghunathan, and N. K. Jha, ``Use of computation-unit integrated memories in high-level synthesis,'' IEEE Transactions on Computer-Aided Design, October 2006.

  35. L. Zhong, S. Ravi, A. Raghunathan, and N. K. Jha, ``RTL-aware cycle-accurate functional power estimation,'' IEEE Transactions on Computer-Aided Design, October 2006.

  36. F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, ``A scalable synthesis methodology for application-specific processors,'' IEEE Transactions on VLSI Systems, November 2006.

  37. D. Arora, S. Ravi, A. Raghunathan, and N. K. Jha, ``Hardware-assisted run-time monitoring for secure program execution on embedded processors,'' IEEE Transactions on VLSI Systems, December 2006.

  38. A. Muttreja, A. Raghunathan, S. Ravi, and N. K. Jha, ``Automated energy/performance macromodeling of embedded software,'' IEEE Transactions on Computer-Aided Design, March 2007.

  39. N. Aaraj, S. Ravi, A. Raghunathan, and N. K. Jha, ``Hybrid architectures for efficient and accurate face authentication in embedded systems,'' IEEE Transactions on VLSI Systems, Mar. 2007.

  40. N. Potlapally, A. Raghunathan, S. Ravi, N. K. Jha, and R. B. Lee, ``Aiding side-channel attacks on cryptographic software with satisfiability-based analysis,'' IEEE Transactions on VLSI Systems, Apr. 2007.

  41. D. Arora, A. Raghunathan, S. Ravi, and N. K. Jha, ``Architectural support for run-time validation of program data properties,'' IEEE Transactions on VLSI Systems, May 2007.

  42. N. R. Potlapally, S. Ravi, A. Raghunathan, R. B. Lee and N. K. Jha, ``Configuration and extension of embedded processors to optimize IPSec protocol execution,'' IEEE Transactions on VLSI Systems, May 2007.

  43. D. Arora, A. Raghunathan, S. Ravi, and N. K. Jha, ``Exploring software partitions for fast security processing on a multiprocessor mobile SoC,'' IEEE Transactions on VLSI Systems, June 2007.

  44. A. Muttreja, A. Raghunathan, S. Ravi, and N. K. Jha, ``Hybrid simulation for energy estimation of embedded software,'' IEEE Transactions on Computer-Aided Design, Oct. 2007.

  45. C. Huang, S. Ravi, A. Raghunathan, and N. K. Jha, ``Generation of heterogeneous distributed architectures for memory-intensive applications through high-level synthesis,'' IEEE Transactions on VLSI Systems, Nov. 2007.

  46. F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, ``A synthesis methodology for hybrid custom instruction and co-processor generation for extensible processors,'' IEEE Transactions on Computer-Aided Design, Nov. 2007.

  47. Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, ``Energy-optimizing source code transformations for operating system driven embedded software,'' ACM Transactions on Embedded Computing Systems, Dec. 2007.

  48. K. Sekar, K. Lahiri, A. Raghunathan, and S. Dey, ``Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication,'' IEEE Transactions on VLSI Systems, October 2008.

  49. D. Gizopoulos, M. Psarakis, M. Hatzimihail, M. Maniatakos, A. Paschalis, A. Raghunathan, and S. Ravi, ``Systematic Software-Based Self-Test for Pipelined Processors,'' IEEE Transactions on VLSI Systems, November 2008.

  50. N. Aaraj, A. Raghunathan, S. Ravi, and N. K. Jha, ``Analysis and design of a software-based trusted platform module for embedded systems," ACM Trans. on Embedded Computing Systems, Dec. 2008.

  51. S. Chandra, K. Lahiri, A. Raghunathan, and S. Dey, ``Variation-Tolerant Dynamic Power Management at the System-Level,'' IEEE Transactions on VLSI Systems, September 2009.

  52. S. Chandra, K. Lahiri, A. Raghunathan, and S. Dey, ``Variation-Aware System-Level Power Analysis,'' IEEE Transactions on VLSI Systems, August 2010.

  53. N. Aaraj, A. Raghunathan, and N. K. Jha, ``A framework for defending embedded systems against software attacks," accepted for publication in ACM Trans. on Embedded Computing Systems.

  54. S. Chandra, K. Lahiri, A. Raghunathan, and S. Dey, ``Variation-Aware Voltage Level Selection,'' accepted for publication in IEEE Transactions on VLSI Systems.

  55. C. Li, A. Raghunathan, and N. K. Jha, "A Trusted Virtual Machine in an Untrusted Management Environment," accepted for publication, IEEE Transactions on Services Computing.

CONFERENCES

  1. A. Raghunathan and N. K. Jha, "Behavioral Synthesis for Low Power", International Conference on Computer Design, October 1994.

  2. A. Raghunathan, P. Ashar, and S. Malik, "Test generation for cyclic combinational circuits", 8th International Conference on VLSI Design, January 1995.

  3. A. Raghunathan and N. K. Jha, "An ILP formulation for minimizing switched capacitance during datapath allocation", International Symposium on Circuits & Systems, May 1995.

  4. S. T. Chakradhar and A. Raghunathan, "Bottleneck elimination algorithm for dynamic compaction and test cycles reduction", European Conference on Design Automation, September 1995.

  5. I. Ghosh, A. Raghunathan, and N. K. Jha, "Design-for-hierarchical-testability of register-transfer level circuits obtained through behavioral synthesis", International Conference on Computer Design, October 1995.

  6. A. Raghunathan and N. K. Jha, "Iterative improvement algorithm for low power datapath synthesis", IEEE/ACM International Conference on Computer-Aided Design, November 1995.

  7. A. Raghunathan and S. T. Chakradhar, "Acceleration techniques for dynamic vector compaction", IEEE/ACM International Conference on Computer-Aided Design, November 1995.

  8. A. Raghunathan and S. T. Chakradhar, "Dynamic test sequence compaction for sequential circuits", 9th International Conference on VLSI Design, January 1996.

  9. A. Raghunathan, S. Dey, and N. K. Jha, "Glitch analysis and reduction in register transfer level power optimization", 33rd ACM/IEEE Design Automation Conference, June 1996 (Best Paper Award Nomination).

  10. G. Lakshminarayana, A. Raghunathan, and N. K. Jha, "Behavioral Synthesis of Fault Secure Controller/Datapaths using Aliasing Probability Analysis", 26th Fault-Tolerant Computing Symposium, June 1996.

  11. A. Raghunathan, S. Dey, and N. K. Jha, "Controller re-specification to minimize switching activity in controller/datapath circuits", International Symposium on Low Power Electronics and Design, August 1996.

  12. I. Ghosh, A. Raghunathan, and N. K. Jha, "A Design for Testability Technique for RTL Circuits Using Control/Data Flow Extraction", IEEE/ACM International Conference on Computer-Aided Design, November 1996.

  13. A. Raghunathan, S. Dey, and N. K. Jha, "Register-Transfer Level Estimation Techniques for Switching Activity and Power Consumption", IEEE/ACM International Conference on Computer-Aided Design, November 1996.

  14. A. Raghunathan, S. Dey, N. K. Jha, and K. Wakabayashi, "Power Management Techniques for Control-Flow Intensive Designs", 34th ACM/IEEE Design Automation Conference, June 1997. (Best Paper Award Nomination)

  15. I. Ghosh, A. Raghunathan, and N. K. Jha, "Hierarchical Test Generation and Design for Testability of ASIPs and ASPPs", 34th ACM/IEEE Design Automation Conference, June 1997.

  16. G. Lakshminarayana, A. Raghunathan, N. K. Jha, and S. Dey, "A power management methodology for high-level synthesis", 11th International Conference on VLSI Design, January 1998. (Prof. A. K. Choudhury Memorial Best Paper Award)

  17. S. Dey, A. Raghunathan, and R. K. Roy, "Considering testability during high-level design", Asia and South Pacific Design Automation Conference (ASP-DAC), February 1998.

  18. M. Lajolo, A. Raghunathan, S. Dey, L. Lavagno, and A. L. Sangiovanni-Vincentelli, "A case study on modeling shared memory access effects during performance analysis of HW/SW systems", 6th International Workshop on Hardware/Software Co-Design (CODES/CASHE'98), March 1998.

  19. G. Lakshminarayana, A. Raghunathan, and N. K. Jha, "Incorporating speculative execution into scheduling of control-flow intensive behavioral descriptions", 35th ACM/IEEE Design Automation Conference, June 1998.

  20. G. Lakshminarayana, A. Raghunathan, N. K. Jha, and S. Dey, "Transforming control-flow intensive designs to facilitate power management", IEEE/ACM International Conference on Computer-Aided Design, November 1998.

  21. P. Ashar, S. Bhattacharya, A. Raghunathan, and A. Mukaiyama, "Verification of RTL generated from scheduled behavior in a high-level synthesis flow", IEEE/ACM International Conference on Computer-Aided Design, November 1998.

  22. M. Lajolo, A. Raghunathan, S. Dey, L. Lavagno, and A. L. Sangiovanni-Vincentelli, "Efficient Power Estimation Techniques for HW/SW System-on-Chip Designs", IEEE Alessandro Volta Memorial International Workshop on Low Power Design, March 1999. (Please see our subsequent DATE 2000 publication listed below)

  23. G. Lakshminarayana, A. Raghunathan, K. S. Khouri, N. K. Jha, and S. Dey, "Common-case computation: A high-level power optimization technique", 36th ACM/IEEE Design Automation Conference, June 1999. (Best Paper Award)

  24. P. Ashar, A. Raghunathan, A. Gupta, and S. Bhattacharya, "Verification of Scheduling in the Presence of Loops Using Uninterpreted Symbolic Simulation", IEEE International Conference on Computer Design, October 1999.

  25. K. Lahiri, A. Raghunathan, and S. Dey, "Fast Performance Analysis of Bus-based SOC Integration/Communication Architectures", IEEE/ACM International Conference on Computer-Aided Design, November 1999.

  26. K. Lahiri, A. Raghunathan, and S. Dey, "Performance Analysis of Systems with Multi-Channel Communication Architectures", IEEE International Conference on VLSI Design, January 2000.

  27. M. Lajolo, A. Raghunathan, S. Dey, and L. Lavagno, "Efficient Power Co-Estimation Techniques for System-on-Chip Designs", IEEE Design and Test Europe (DATE), March 2000.

  28. K. Lahiri, A. Raghunathan, G. Lakshiminarayana, and S. Dey, "Communication Architecture Tuners: A Methodology for the Design of High-Performance Communication Architectures for System-on-Chips", ACM/IEEE Design Automation Conference, June 2000. (Best Paper Award)

  29. R. P. Dick, G. Lakshiminarayana, A. Raghunathan, and N. K. Jha, "Power Analysis of Embedded Operating Systems", ACM/IEEE Design Automation Conference , June 2000.

  30. K. Lahiri, A. Raghunathan, S. Dey, "Efficient Exploration of the SoC Communication Architecture Design Space", IEEE/ACM International Conference on Computer-Aided Design, November 2000.

  31. N. R. Potlapally, A. Raghunathan, G. Lakshminarayana, M. S. Hsiao, and S. T. Chakradhar, "Accurate power macro-modeling techniques for complex RTL circuits", IEEE International Conference on VLSI Design, January 2001.

  32. D. Panigrahi, C. Chiasserini, S. Dey, R. Rao, A. Raghunathan, and K. Lahiri, "Battery life estimation of mobile embedded systems", IEEE International Conference on VLSI Design, January 2001.

  33. K. Lahiri, A. Raghunathan, and S. Dey, "Evaluation of the traffic-performance characteristics of system-on-chip communication architectures", IEEE International Conference on VLSI Design , January 2001.

  34. D. Panigrahi, A. Raghunathan, G. Lakshminarayana, and S. Dey, "Energy Modeling for Wireless Internet Access," IEEE International Conference on Third Generation Wireless and Beyond (3G Wireless '01), May 2001.

  35. K. Lahiri, A. Raghunathan, and G. Lakshminarayana, "LOTTERYBUS: A novel high-performance communication architecture for system-on-chip designs," ACM/IEEE Design Automation Conference (DAC), June 2001.

  36. T. K. Tan, A. Raghunathan, G. Lakshminarayana, and N. K. Jha, "High-level software energy macromodeling," ACM/IEEE Design Automation Conference (DAC), June 2001.

  37. W. Wang, A. Raghunathan, G. Lakshminarayana, and N. K. Jha, "Input Space Adaptive Design: A high-level methodology for energy and performance optimization," ACM/IEEE Design Automation Conference (DAC), June 2001.

  38. V. Raghunathan, S. Ravi, A. Raghunathan, and G. Lakshminarayana, "Transient power management through high-level synthesis", IEEE/ACM International Conference on Computer-Aided Design, November 2001.

  39. K. Lahiri, A. Raghunathan, S. Dey, and D. Panigrahi, "Battery-driven system design: A new frontier in low power design", Asia South Pacific Design Automation Conference (ASP-DAC) / International Conference on VLSI Design, January 2002.

  40. W. Wang, A. Raghunathan, G. Lakshminarayana, and N. K. Jha, "Input space adaptive embedded software synthesis", Asia South Pacific Design Automation Conference (ASP-DAC) / International Conference on VLSI Design, January 2002.

  41. V. Raghunathan, A. Raghunathan, M. Srivastava, and M. D. Ercegovac, "High-level synthesis with SIMD units", Asia South Pacific Design Automation Conference (ASP-DAC) / International Conference on VLSI Design, January 2002.

  42. N. Potlapally, S. Ravi, A. Raghunathan, and G. Lakshminarayana, "Algorithm exploration for efficient public-key security processing on wireless handsets," Design, Automation and Test in Europe (DATE), March 2002.

  43. K. Lahiri, A. Raghunathan, and S. Dey, "Battery-efficient architecture for an 802.11 MAC processor", IEEE International Conference on Communications (ICC), May 2002.

  44. N. Potlapally, S. Ravi, A. Raghunathan, and G. Lakshminarayana, "Optimizing public-key encryption for wireless clients", IEEE International Conference on Communications (ICC), May 2002.

  45. D. Panigrahi, S. Dey, and A. Raghunathan, "Network Aware Content Shaping for Energy Efficient Wireless Web Access", IEEE Workshop on Integrated Management of Power Aware Communications, Computing and Networking (IMPACCT), May 2002.

  46. T. K. Tan, A. Raghunathan, and N. K. Jha, "EMSIM: An energy simulation framework for an embedded operating system," IEEE International Symposium on Circuits and Systems (ISCAS), May 2002.

  47. J. Chang, S. Ravi, and A. Raghunathan, "FLEXBAR: A crossbar switching fabric with improved performance and utilization," IEEE Custom Integrated Circuits Conference (CICC), May 2002. [Links to EE Times coverage of FLEXBAR: "Innovative ideas leap design hurdles at CICC", "Flexible I/O speeds data switch"]

  48. K. Lahiri, A. Raghunathan, and S. Dey, "Fast system-level power profiling for battery efficient HW/SW system design," IEEE Int. Symp. on Hardware/Software Codesign (CODES), May 2002.

  49. S. Ravi, A. Raghunathan, N. Potlapally, and M. Sankaradass, "System design methodologies for a wireless security processing platform", ACM/IEEE Design Automation Conference (DAC), June 2002.

  50. K. Lahiri, A. Raghunathan, and S. Dey, "Communication architecture based power management for battery efficient system design", ACM/IEEE Design Automation Conference (DAC), June 2002. (One of five papers chosen as "Best of Practice at DAC")

  51. T. K. Tan, A. Raghunathan, and N. K. Jha, "Energy macromodeling of embedded operating systems," IEEE International Conference on Computer Design (ICCD), October 2002.

  52. S. Ravi, A. Raghunathan, and N. Potlapally, "Securing wireless data: System Architecture Challenges," IEEE International Symposium on System Synthesis (ISSS), October 2002. (Invited paper)

  53. F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, "Synthesis of custom processors based on extensible platforms," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2002.

  54. C. Huang, S. Ravi, A. Raghunathan, and N. K. Jha, "High-level synthesis of distributed logic-memory architectures," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2002.

  55. S. Ravi, A. Raghunathan, and S. T. Chakradhar, "Efficient RTL Power Estimation for Large Designs," IEEE International Conference on VLSI Design, January 2003. (Best Paper Award - General category)

  56. W. Wang, A. Raghunathan, N. K. Jha, and S. Dey, "High-level synthesis of multi-process behavioral descriptions," IEEE International Conference on VLSI Design, January 2003. (Best Paper Award - Student co-authored category)

  57. S. Ravi, A. Raghunathan, and S. T. Chakradhar, "Embedding Security in Wireless Embedded Systems," IEEE International Conference on VLSI Design, January 2003.

  58. Y. Fei, S. Ravi, A. Raghunathan, N. K. Jha, "Energy Estimation for Extensible Processors," Design, Automation, and Test in Europe (DATE), March 2003.

  59. T. K. Tan, A. Raghunathan, and N. K. Jha, "Software Architectural Transformations: A new approach to low power embedded software," Design, Automation, and Test in Europe (DATE), March 2003.

  60. D. Bertozzi, A. Raghunathan, S. Ravi, and L. Benini, "Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems," Design, Automation, and Test in Europe (DATE), March 2003.

  61. A. Raghunathan, S. Ravi, S. Hattangady, and J.-J Quisquater, "Securing Mobile Appliances: New Challenges for the System Designer," Design, Automation, and Test in Europe (DATE), March 2003. (Invited paper - hot topic session)

  62. W. Wang, T. K. Tan, J. Luo, Y. Fei, L. Shang, K. S. Vallerio, L. Zhong, A. Raghunathan, and N. K. Jha, "A Comprehensive High-level Synthesis System for Control-flow Intensive Behaviors," Great Lakes Symposium on VLSI, March 2003.

  63. L. Chen, S. Ravi, A. Raghunathan, and S. Dey, "A Scalable Software-based Self-test Methodology for Programmable Processors," ACM/IEEE Design Automation Conference, June 2003. (Best Paper Award Nomination)

  64. N. R. Potlapally, S. Ravi, A. Raghunathan, and N. K. Jha, "Analyzing the energy consumption of security protocols," IEEE Int. Symp. on Low Power Electronics and Design, August 2003.

  65. F. Sun, A. Raghunathan, S. Ravi, and N. K. Jha, "A scalable application-specific processor synthesis methodology," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2003.

  66. C. Huang, S. Ravi, A. Raghunathan, and N. K. Jha, "Synthesis of distributed heterogeneous architectures for memory-intensive applications," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2003.

  67. W. Wang, A. Raghunathan, and N. K. Jha, "Profiling driven computation re-use: An embedded software synthesis technique for energy and performance optimization," IEEE International Conference on VLSI Design, January 2004.

  68. Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, "Energy-optimizing source code transformations for OS-driven embedded software," IEEE International Conference on VLSI Design, January 2004.

  69. S. Ravi, A. Raghunathan, and S. T. Chakradhar, "Tamper-resistant embedded system design," IEEE International Conference on VLSI Design, January 2004.

  70. T. K. Tan, A. Raghunathan, and N. K. Jha, "An energy-aware synthesis methodology for OS-driven multi-process embedded software," International Conference on Embedded Systems and Applications, June 2004.

  71. P. Kocher, R. Lee, G. McGraw, A. Raghunathan, and S. Ravi, "Security as a new dimension in embedded system design," ACM/IEEE Design Automation Conference, June 2004.

  72. A. Muttreja, A. Raghunathan, S. Ravi, and N. K. Jha, "Automated energy/performance macromodeling of embedded software," ACM/IEEE Design Automation Conference, June 2004.

  73. K. Lahiri and A. Raghunathan, "Power analysis of system-level on-chip communication architectures," International Symposium on Hardware/Software Codesign and System Synthesis, September 2004.

  74. L. Zhong, S. Ravi, A. Raghunathan, and N. K. Jha, "Power estimation for cycle-accurate functional descriptions of hardware," IEEE/ACM International Conference on Computer-Aided Design, November 2004.

  75. C. Huang, S. Ravi, A. Raghunathan, and N. K. Jha, "High-level synthesis using computation unit integrated memories," IEEE/ACM International Conference on Computer-Aided Design, November 2004.

  76. F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, "Synthesis of application-specific heterogeneous multiprocessor architectures using extensible processors," IEEE International Conference on VLSI Design, January 2005.

  77. L. Lingappan, S. Ravi, A. Raghunathan, N. K. Jha, and S. T. Chakradhar, "Heterogeneous and multi-level compression techniques for test volume reduction in system-on-chips," IEEE International Conference on VLSI Design, January 2005.

  78. K. Lahiri, N. Bansal, A. Raghunathan, and S. T. Chakradhar, "A monitor-based framework for system-level power estimation using heterogeneous power models," IEEE International Conference on VLSI Design, January 2005.

  79. D. Arora, S. Ravi, A. Raghunathan, and N. K. Jha, "Secure embedded processing through hardware-assisted run-time monitoring," Design, Automation, and Test in Europe (DATE), March 2005.

  80. J. Coburn, S. Ravi and A. Raghunathan, "Hardware-accelerated power estimation," Design, Automation, and Test in Europe (DATE), March 2005.

  81. K. Sekar, K. Lahiri, A. Raghunathan, and S. Dey, "FLEXBUS: A high-performance system-on-chip communication architecture with a dynamically configurable topology," ACM/IEEE Design Automation Conference, June 2005.

  82. P. Gupta, S. Ravi, A. Raghunathan, and N. K. Jha, "Efficient and secure fingerprint-based user authentication for embedded systems," ACM/IEEE Design Automation Conference, June 2005.

  83. A. Muttreja, A. Raghunathan, S. Ravi, and N. K. Jha, "Hybrid simulation for embedded software energy estimation," ACM/IEEE Design Automation Conference, June 2005.

  84. J. Coburn, S. Ravi, and A. Raghunathan, "Power emulation: A new paradigm for power estimation," ACM/IEEE Design Automation Conference, June 2005.

  85. C. Huang, S. Ravi, A. Raghunathan, and N. K. Jha, "Eliminating memory bottlenecks for a JPEG encoder through distributed logic-memory architecture and computation-unit integrated memory," IEEE Custom Integrated Circuits Conference (CICC), September 2005.

  86. D. Arora, S. Ravi, A. Raghunathan, and N. K. Jha, "Enhancing security through hardware-assisted run-time validation of program data properties," International Conference on Hardware-Software Codesign and System Synthesis (CODES/ISSS), September 2005.

  87. J. Coburn, S. Ravi, A. Raghunathan, and Srimat Chakradhar, "Security-enhanced communication architecture," ACM/IEEE Conf. on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), September 2005.

  88. C. Park, K. Lahiri, and A. Raghunathan, "Battery discharge characteristics of wireless sensor nodes: An experimental analysis," IEEE Conf. on Sensor and Ad-hoc Communications and Networks (SECON), September 2005.

  89. N. R. Potlapally, S. Ravi, A. Raghunathan, R. B. Lee, and N. K. Jha, "Impact of configurability and extensibility on IPSec protocol execution on embedded processors," IEEE Int. Conf. on VLSI Design, January 2006.

  90. F. Sun, A. Raghunathan, S. Ravi, and N. K. Jha, "Hybrid custom instruction and co-processor synthesis methodology for extensible processors," IEEE Int. Conf. on VLSI Design, January 2006.

  91. N. Aaraj, S. Ravi, A. Raghunathan, and N. K. Jha, "Architectures for efficient face authentication in embedded systems," Design, Automation, and Test in Europe (DATE), March 2006.

  92. N. Potlapally, A. Raghunathan, S. Ravi, N. K. Jha, and R. B. Lee, "A satisfiability-based framework for side-channel attacks on cryptographic software," Design, Automation, and Test in Europe (DATE), March 2006.

  93. P. Stanley-Marbell, K. Lahiri, and A. Raghunathan, "An application-adaptive thread library for embedded multiprocessors," Design, Automation, and Test in Europe (DATE), March 2006.

  94. K. Sekar, K. Lahiri, A. Raghunathan, and S. Dey, "Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms," Design, Automation, and Test in Europe (DATE) , March 2006.

  95. G. Tan, A. W. Appel, S. T. Chakradhar, A. Raghunathan, S. Ravi, and D. Wang, "Safe Java Native Interface," IEEE Int. Symp. on Secure Software Engineering (ISSSE), March 2006.

  96. A. Muttreja, S. Ravi, A. Raghunathan, and N. K. Jha, "Active learning driven data acquisition for sensor networks," IEEE Symposium on Computers and Communications, June 2006.

  97. D. Arora, A. Raghunathan, S. Ravi, M. Sankaradass, N. K. Jha, and S. T. Chakradhar, "Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC," ACM/IEEE Design Automation Conference, July 2006.

  98. M. Psarakis, D. Gizopoulos, M. Hatzimihail, A. Paschalis, A. Raghunathan, and S. Ravi, "Systematic sotware-based self-test for pipelined processors," ACM/IEEE Design Automation Conference, July 2006.

  99. S. Chandra, K. Lahiri, A. Raghunathan, S. Dey, ``Considering Process Variations During System-level Power Analysis", Int. Symp. Low Power Electronics and Design (ISLPED), October 2006.

  100. D. Arora, A. Raghunathan, S. Ravi, and N. K. Jha, ``Architectural support for safe software execution on embedded processors,'' ACM/IEEE Int. Conf. on HW/SW Co-design and System Synthesis, October 2006. (Best Paper Award)

  101. N. Bansal, K. Lahiri, and A. Raghunathan, ``Automatic Power Modeling of System-on-Chip Infrastructure IP for System-level Power Analysis", Intl. Conf. on VLSI Design, January 2007.

  102. N. Aaraj, A. Raghunathan, S. Ravi, and N. K. Jha, ``Energy and execution time analysis of a software-based trusted platform module,'' IEEE Design Automation and Test in Europe (DATE), April 2007.

  103. M. A. Ghodrat, K. Lahiri, A. Raghunathan, ``Acelerating System-on-Chip Power Analysis Using Hybrid Power Estimation," ACM/IEEE Design Automation Conference, June 2007.

  104. S. Chandra, K. Lahiri, A. Raghunathan, and S. Dey, ``System-on-Chip Power Management Considering Leakage Power Variations," ACM/IEEE Design Automation Conference, June 2007.

  105. J. Thoguluva, A. Raghunathan, and S. T. Chakradhar, ``Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor,'' IEEE Design Automation and Test in Europe (DATE), April 2008.

  106. N. Aaraj, A. Raghunathan, and N. K. Jha, ``Dynamic binary instrumentation based framework for malware (virus) defense," Conf. on Detection of Intrusions and Malware and Vulnerability Assessment, July 2008.

  107. N. Banerjee, S. Chandra, S. Ghosh, S. Dey, A. Raghunathan, and K. Roy, "Coping with Variations through System-Level Design", Invited Embedded tutorial, International Conference on VLSI Design , January 2009.

  108. C. Li, A. Raghunathan, and N. K. Jha, ``An architecture for secure software defined radio," Design Automation and Test Europe, March 2009.

  109. J. Meng, S. T. Chakradhar, and A. Raghunathan, "Best-effort parallel execution framework for recognition and mining applications", IEEE International Parallel & Distributed Processing Symposium, May 2009.

  110. N. Sundaram, A. Raghunathan, and S. T. Chakradhar, "A framework for efficient and scalable execution of domain-specific templates on GPUs", IEEE International Parallel & Distributed Processing Symposium, May 2009.

  111. K. Roy, B. Jung, and A. Raghunathan, ``Integrated systems in the more-than-Moore era: Designing low-cost energy-efficient systems using heterogeneous components," IEEE International Conference on VLSI Design, January 2010.

  112. S. Byna, S. T. Chakradhar, S. Cadambi, J. Meng, and A. Raghunathan, "Best effort Semantic Document Search on GPUs," Third Workshop on General-Purpose Computation on Graphics Processing Units, March 2010.

  113. J. Meng, A. Raghunathan, S. T. Chakradhar, and S. Byna, "Exploiting the forgiving nature of applications for scalable parallel execution", IEEE International Parallel & Distributed Processing Symposium, April 2010.

  114. V. Chippa, D. Mohapatra, A. Raghunathan, K. Roy, and S. T. Chakradhar, "Scalable Effort Hardware: Exploiting Algorithmic Resiliency for Energy Efficiency", ACM/IEEE Design Automation Conference, June 2010.

  115. S. T. Chakradhar and A. Raghunathan, "Best-effort computing: Rethinking parallel hardware and software", ACM/IEEE Design Automation Conference, June 2010.

  116. J.-W. Chuah, A. Raghunathan, and N. K. Jha, ``An evaluation of energy-saving technologies for residential purposes," IEEE Power Engineering Society General Meeting, July 2010.

  117. C. Li, A. Raghunathan, and N. K. Jha, ``Secure virtual machine execution under an untrusted management OS," IEEE International Conference on Cloud Computing, July 2010.(Best Paper Award)

  118. C. Li, A. Raghunathan, and N. K. Jha, ``A secure user interface for web applications running under an untrusted operating system," IEEE International Conference on Computer and Information Technology, June 2010.

  119. D. Mohapatra, V. Chippa, K. Roy, and A. Raghunathan, ``Design of voltage-scalable meta functions for approximate computing," IEEE/ACM Design, Automation, and Test in Europe, March 2011.

  120. V. Kozhikkottu, R. Venkatesan, A. Raghunathan, and S. Dey, ``VESPA: Variability Emulation for System-on-chip Performance Analysis," IEEE/ACM Design, Automation, and Test in Europe, March 2011.

  121. J. Pienaar, A. Raghunathan, and S. T. Chakradhar, "MDR: Performance Model Driven Runtime for Heterogeneous Parallel Platforms," ACM International Conference on Supercomputing (ICS), May-June 2011.

  122. V. Rangharajan, A. Agarwal, A. Raghunathan, and K. Roy, "Modeling and Analysis of Circuits for Approximate Computing", Work-in-Progress Session, ACM/IEEE Design Automation Conference, June 2011.

  123. V. Chippa, A. Raghunatha, K. Roy, and S. T. Chakradhar, "Dynamic Effort Scaling: Managing the Quality-Efficiency Tradeoff", ACM/IEEE Design Automation Conference, June 2011.

  124. V. Rangharajan, V. Chippa, C. Augustine, A. Raghunathan, and K. Roy, "Energy Efficient Many-core Processor for Recognition and Mining using Spin-based Memory," IEEE/ACM International Symposium on Nanoscale Architectures, June 2011.

  125. C. Li, A. Raghunathan, and N. K. Jha, "Hijacking an insulin pump: Security attacks and defenses for a diabetes therapy system", IEEE International Conference on e-Health Networking, Application and Services (Healthcom), June 2011.

  126. V. Rangharajan, A. Agarwal, K. Roy, and A. Raghunathan, "MACACO: Modeling and Analysis of Circuits for Approximate Computing," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), November 2011.