Note: All of the patents listed here are U.S patents. However, some of these inventions have also been patented in other countries. Here are links to my patents on Google Patent Search and the US Patent Office

  1. Anand Raghunathan and Srimat T. Chakradhar, "Process for Dynamic Compaction and Test Cycles Reduction," U.S patent No. 5,726,996, issued 3/10/1998.

  2. Anand Raghunathan and Niraj K. Jha, "Design Tools for High-Level Synthesis of a Low Power Data Path," U.S patent No. 5,831,864, issued 11/1998.

  3. Anand Raghunathan, Sujit Dey, and Niraj K. Jha, "Controller-based Power Management Methodology for Low-Power VLSI Design," U.S patent No. 6,105,139 , issued 08/15/2000.

  4. Pranav Ashar, Subhrajit Bhattacharya, Anand Raghunathan, and Akira Mukaiyama, "Method for verification of RTL generated from scheduled behavior in a high-level synthesis flow," U.S patent No. 6,163,876 , issued 12/19/2000.

  5. Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, and Sujit Dey, "Constrained Register Sharing Technique for Low-Power VLSI Design," U.S patent No. 6,195,786 , issued 02/27/2001.

  6. Anand Raghunathan and Ganesh Laksminarayana, "Common case optimized circuit structure for high-performance and low-power VLSI designs," U.S patent No. 6,275,959, issued 08/14/2001.

  7. Ganesh Laksminarayana, Anand Raghunathan, Kamal S. Khouri, and Niraj K. Jha, "Method for synthesis of common case optimized circuits to improve performance and power dissipation," U.S patent No. 6,308,313, issued 10/23/2001.

  8. Anand Raghunathan and Sujit Dey, "Register transfer level power optimization with emphasis on glitch analysis and reduction," U.S patent No. 6,324,679, issued 11/27/2001.

  9. Wolfgang Roethig, Ganesh Lakshminarayana, Anand Raghunathan and Arun Balakrishnan, "Multi-level power macromodeling," U.S patent No. 6,625,781, issued 9/23/2003.

  10. Kanishka Lahiri, Anand Raghunathan, and Ganesh Lakshminarayana, "System for the design of high-performance communication architecture for system-on-chips using communication architecture tuners," U.S patent No. 6,694,488, issued 2/17/2004.

  11. Anand Raghunathan, Ganesh Lakshminarayana, Nachiketh Potlapally, Michael S. Hsiao, and Srimat T. Chakradhar, "Power mode based macro-models for power estimation of electronic circuits," U.S patent No. 6,735,744, issued 5/11/2004.

  12. Pranav Ashar, Anand Raghunathan, Subhrajit Bhattacharya, and Aarti Gupta, "Verification of scheduling in the presence of loops using uninterpreted symbolic simulation," U.S patent No. 6,745,160, issued 6/1/2004.

  13. Kanishka Lahiri, Ganesh Lakshminarayana, and Anand Raghunathan, "High performance communication architecture for circuit designs using probabilistic allocation of resources," U.S patent No. 6,877,053, issued 4/1/2005.

  14. Anand Raghunathan, Ganesh Lakshminarayana, Kanishka Lahiri, and Sujit Dey "Methodology for the design of high-performance communication architectures for system-on-chips using communication architecture tuners," U.S patent No. 6,978,425, issued 12/20/2005.

  15. Srivaths Ravi, Anand Raghunathan, and Srimat T. Chakradhar, "Method and apparatus for efficient register-transfer level (RTL) power estimation," U.S patent No. 7,134,100, issued 11/7/2006.

  16. Srivaths Ravi, Anand Raghunathan, and Jacob Chang, "Flexible crossbar switching fabric," U.S patent No. 7,173,906, issued 2/6/2007.

  17. Srivaths Ravi, Anand Raghunathan, Lin Zhong, and Niraj K. Jha, "Power estimation employing cycle-accurate functional descriptions," U.S patent No. 7,260,809, issued 8/21/2007.

  18. Srivaths Ravi, Anand Raghunathan, Loganathan Lingappan, Srimat Chakradhar, and Niraj K. Jha, "System-level test architecture for delivery of compressed tests," U.S patent No. 7,278,123, issued 10/2/2007.

  19. Srivaths Ravi, Anand Raghunathan, Srimat Chakradhar, and Kartik Nandakumar, "Voice-based multimodal speaker authentication using adaptive training and applications thereof," U.S patent No. 7,529,669, issued 5/5/2009.

  20. Srimat Chakradhar, Anand Raghunathan, and Narayanan Sundaram, "Methods and systems for managing computations on a hybrid computing platform including a parallel accelerator," em> U.S patent No. 8,225,074, issued July 17, 2012.

  21. Srimat Chakradhar, Anand Raghunathan, and Jiayuan Meng, "Systems and methods for implementing best-effort parallel computing frameworks," em> U.S patent No. 8,286,172 , issued October 9, 2012.