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Vertical Tri-Gate Power MOSFET on 4H-SiC

Tri-gate (3G) MOSFET is formed from a DMOSFET by etching trenches that run perpendicular to the gate and source fingers. This places a MOS gate over the sidewalls of the p-base implants, creating new channels (yellow arrows) for electrons to flow from the source to the JFET region. This new SiC power MOSFET structure dramatically reduces the MOS channel resistance.

IMOSFET: A Deeply Scaled Fully-self-aligned Trench MOSFET

A critical issue in Trench MOSFETs is the presence of higher field in the gate oxide (Eox) around the bottom of trench affecting the long-term reliability of the device. The self-aligned trench along with the well grounded p+ implant shield in our proposed IMOS ensures a lower Eox, maintaining 2 channels, i.e. higher channel density, and lower channel resistance as promised in vertical devices.

n-channel IGBT

The structure of an IGBT is same as a vertical MOSFET with the exception that the substrate is replaced by the opposite doping polarity. Conceptually, the IGBT is a combination of a bipolar junction transistor (BJT) and a MOSFET. The major bottleneck at this high blocking voltage device is its ON resistance of the drift region which follows a quadratic relationship with the blocking voltage. The insulated gate bipolar transistor (IGBT) is an effective solution because conductivity modulation in the drift region reduces the ON resistance significantly even at high junction temperatures.

Waffled substrate in MOSFETs

The specific ON resistance of IMOSFETs is limited by the substrate resistance. Though thinning the substrate can significantly help, a thinner substrate also compromises on the strength of the device. In our research, we are fabricating devices with hexagonal and circular cavities on the backside of the substrates, resulting in robust bee-hive shaped “waffled substrates” . These promise a specific ON resistance that is 3.5-4x lower than that of the original substrate.