Programmable Accelerator Architectures
- Understand the design of contemporary programmable accelerators (i.e. GPUs) and how the programming model relates to the design.
- Program a GPU using CUDA to perform data parallel tasks and perform performance optimizations on their code, leveraging knowledge of the architectures design.
- Prototype modifications to the architecture using a simulation infrastructure.
- Describe state-of-the-art research in the programmable accelerator space and implement/evaluate those designs in simulation.
- Describe and contrast contemporary machine-learning accelerators with traditional programmable accelerators.
Programmable hardware accelerators seek to fulfill the promise of continued performance and energy-efficiency gains in the era of a slowing Moore's law, larger problem sizes and an increased focused on energy-efficiency. These factors have caused hardware acceleration to become ubiquitous in today's computing world and critically important in computing's future.
This class will introduce students to the architectures of programmable accelerators. We will delve deeply into the architectures of modern massively parallel accelerators like GPUs, culminating in a course project. General topics in hardware acceleration will be discussed, including but not limited to GPGPU and massively parallel computing, approximate accelerators, reconfigurable hardware and programmable hardware for machine learning.
Prerequisites:Previous computer architecture courses, undergraduate or graduate
Applied / Theory:50 / 50
Homework:Two programming assignments, 1-2 quizzes per week.
Exams:One midterm exam; one final exam.
- Aamodt, T.M., Fung, W.L., & Rogers, T.G. 2018. General Purpose Graphics Processor Architecture. Synthesis Lectures on Computer Architecture. Available online through the Purdue Libraries.
- Kirk, D. B., & Hwu, W. M. W.(2016).Programming Massively Parallel Processors: A Hands-on Approach: Third Edition. Elsevier Inc. (Recommended). Available online through the Purdue Libraries.