Jun Huang

Exploring Channel Doping Designs for High-Performance Tunneling FETs

Exploring Channel Doping Designs for High-Performance Tunneling FETs J. Z. Huang, P. Long, M. Povolotskyi, M. J.W. Rodwell, and G. Klimeck

Problem:

  • ON/OFF ratio of tunnel field-effect transistors (TFETs) is limited by
    1. low source-to-channel tunneling probability.
    2. high source-to-drain tunneling leakage.
  • Lowering the drain doping density (Nd) suppresses the leakage but is not scable.
  • The source-pocket (SP) design improves the tunnel probability but requires a high pocket doping density (Np)

Objective:

  • To explore different channel doping strategies to improve ON current of TFETs

Approaches:

  • D1, a conventional nTFET with intrinsic channel
  • D2, intrinsic channel with a P+ drain pocket
  • D3, P+ channel with an intrinsic source pocket
  • D4, P+ channel with an N+ source pocket

Results/Impact:

  • D2 improves the subthreshold swing (and ION) and it is more scalable than lowering Nd
  • D3 performs similarly to the SP design
  • D4 further improves ION of the SP design without having to increase Np
  • D2, D3, and D4 improve the ION of D1 from 25A/m to 43A/m, 114A/m, and 170A/m, respectively, at IOFF=10^-3A/m and VDD=0.3V
  • in Proc. 74th Annu. Device Res. Conf. (DRC), Jun. 2016.